Explain why set_voltage's max-delay number is the lower voltage in a corner pair, connecting it to STA fundamentals.

Short Answer

A max-delay corner is the worst-case setup condition — the slowest the design can legally run. Lower supply voltage gives a transistor less drive current, so switching is slower and delay is larger. That is why the positional (max-delay) value in set_voltage is the lower voltage in the pair, and the -min value — the min-delay, hold-checking voltage — is the higher one.

Technical Explanation

This connects directly back to the two checks STA runs on every path: setup, which fails if data arrives too late, and hold, which fails if data arrives too early.

• Delay and drive current move together. A CMOS gate's switching speed depends on how much current its transistors can source or sink — higher supply voltage gives more overdrive, pushes more current, and switches the output faster; lower voltage means less current and a longer delay.
• Max-delay analysis wants the slowest condition. "Max-delay" is PrimeTime's (PT) term for the setup-checking corner — the tool needs the largest possible delay to be sure setup still passes in the worst case, and the slowest condition is the lowest voltage in the range.
• Min-delay analysis wants the fastest condition. "Min-delay" is the hold-checking corner — the tool needs the smallest possible delay so data cannot race ahead of the capturing edge, and the fastest condition is the highest voltage in the range.
• set_voltage (PT) syntax follows this, with no -max flag. The command is set_voltage value -min value -object_list [get_supply_nets ...], where the plain positional value sets the max-delay voltage and -min sets the min-delay voltage — the option name refers to the analysis type, not to a small number, which is why it legally carries the larger value.
• The guide states this outcome directly: set_voltage 0.8 -min 1.2 VDD sets the supply to 0.8 V for maximum-delay analysis and 1.2 V for minimum-delay analysis.
• Why this trips people up: reading "-max" and "-min" as maximum-value and minimum-value is backwards here — they name which delay check the voltage feeds, not the size of the number.
• One honest exception: near the threshold voltage, temperature inversion can make a hot chip switch faster than a cold one, but that reverses the temperature relationship, not the voltage one — the low voltage in a pair stays the max-delay corner regardless.

Follow-up Question & Model Response

"How does temperature inversion complicate this voltage rule?"

Candidate Model Response: At advanced nodes, near-threshold voltages can make a transistor's delay increase as temperature drops instead of the usual decrease — that is temperature inversion, and it means the traditional slow corner (low voltage, high temperature) is not automatically the true worst case at every node. But that effect concerns temperature, not voltage: for a fixed temperature, lower voltage still gives less drive current and a longer delay. The set_voltage max-delay-is-lower-voltage rule still holds; what changes is which temperature you pair with that voltage to find the true worst case, so a rigorous signoff checks both a low-temperature and a high-temperature reading at the same low voltage rather than assuming one is always worse.