How do you model and verify timing across multiple clock domains with different frequencies (e.g., a 2:1 frequency crossing)?

Short Answer

A frequency-divided relationship between two clocks — say a 2:1 crossing where one domain runs at half the frequency of another — is modeled with a generated clock: a clock definition that derives its edges from a source clock using a stated divide ratio, instead of an independent create_clock on the same physical clock pin. That lets the tool compute the exact synchronous relationship between every edge of both clocks, rather than treating the crossing as an unrelated, asynchronous boundary.

Technical Explanation

• create_clock (SDC) defines a completely independent clock waveform at a pin. If the divided clock were defined this way, the tool would have no idea the two clocks are phase-related, and it would fall back on the least-common-multiple expansion of both periods to search for a valid alignment — often finding none, and marking the whole crossing as unconstrained.
• create_generated_clock (SDC) instead ties the new clock's edges to a source clock through an explicit relationship: -divide_by N for a frequency divider, -multiply_by N for a multiplier, or -edges {...} for an arbitrary edge-derived waveform (for example, a pulse generated off specific rising and falling source edges).
• For a straightforward 2:1 divider off a flip-flop output, the command names the divide ratio and the source clock: create_generated_clock -name CLK_DIV2 -source [get_ports CLK] -divide_by 2 [get_pins FF1/Q] (SDC). The tool then derives CLK_DIV2's period, edges, and phase directly from CLK, rather than requiring a second independent waveform.
• Because both clocks now trace back to one source, the tool can compute the exact worst-case alignment between any launch edge of one and any capture edge of the other across the full common period (the least common multiple of both periods), instead of assuming an arbitrary phase relationship.
• For crossings that are not built from a plain frequency divider — say a clock derived from specific falling edges of the source, rather than every other rising edge — -edges (SDC) states exactly which source edges produce the derived clock's rising and falling transitions, so the phase relationship stays exact rather than being approximated.
• What breaks if the relationship is defined as two independent create_clocks instead: the tool cannot exploit the known phase relationship, so it either treats the crossing as false (missing real timing risk) or reports overly pessimistic multi-cycle timing across every possible LCM-period alignment, wasting margin the real logic never needs.

Follow-up Question & Model Response

"Once CLK and CLK_DIV2 are both generated-clock-related, how does the tool decide which edge pairing is the worst case for a setup check between them?"

Candidate Model Response: The tool expands both clocks over their common period — the least common multiple of the two periods — and enumerates every valid launch-edge, capture-edge pairing that a real signal transition could use. For each launch edge on the faster clock it finds the nearest following capture edge on the slower clock and computes the resulting requirement, then reports the pairing that produces the smallest slack as the setup-critical case. Because CLK_DIV2 is generated from CLK rather than independently defined, this expansion is exact rather than assumed, and it is why -divide_by or -edges needs to match the real gated-clock behavior precisely.