IntermediateQuestion 37 of 112

Why does the setup-check equation subtract the capture clock path but the hold-check equation also subtract it - aren't they opposite checks?

From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide

By Tabish Iqbal, who has 9+ years of VLSI Physical Design experience

Short Answer

Both equations subtract the capture clock's delay term because that delay always shifts the capture edge later in time — a single fact about the circuit. For setup, a later capture edge helps by relaxing the deadline; for hold, it hurts by widening the race window. Same term, same sign, opposite effect on margin.

Setup and hold timing equations side by side with the capture-clock delay term highlighted in both, arrows showing it relaxes the setup deadline but tightens the hold margin — Technical Reference DiagramWhy does the setup-check equation subtract the capture clock path but the hold-check equation also subtract it - aren't they opposite checks?

Technical Reference DiagramWhy does the setup-check equation subtract the capture clock path but the hold-check equation also subtract it - aren't they opposite checks?

Technical Explanation

The sign in the equation and the effect on margin are two different things, and mixing them up is what makes this feel like a contradiction.

The shared physical fact: both checks subtract the capture-clock delay term for the same reason — clock delay to the capture register shifts the capture edge later in time, which widens the window between launch and capture.
Why that's a single, check-independent fact: the clock either arrives late at the capture register or it doesn't; that timing doesn't change depending on which check the tool happens to be running.
What differs is whether the wider window helps: for setup, a later capture edge means the data has more time to arrive before it's needed, so a larger capture-clock delay relaxes the effective period requirement — the check gets easier.
For hold, the same later edge is harmful: it gives the newly launched data more opportunity to arrive and get captured too soon, before the old data was safely read, so a larger capture-clock delay eats into hold margin — the check gets harder.
Same algebraic sign, opposite consequence for margin — that's the actual answer to the question, not a contradiction in the equations.
Why OCV derates the term in opposite directions for the two checks: since a larger capture-clock delay helps setup, conservative setup analysis wants that term scaled down; since it hurts hold, conservative hold analysis wants it scaled up. The derating direction follows from which way makes each check pessimistic, not from the term's sign in the equation.

Common Mistake

The Trap: assuming that because setup and hold are "opposite checks," every term in their equations must carry an opposite sign.

A candidate memorizes the setup and hold equations separately and, on seeing the same term subtracted in both, concludes one of the two must be a misprint.
That misreading leads to guessing the wrong direction when asked to derate the capture-clock term for OCV, scaling it the same way for both checks instead of in opposite directions, which produces an optimistic hold check or an overly pessimistic setup check.

Follow-up Question & Model Response

If a later capture-clock edge always widens the launch-to-capture window, why doesn't the launch-clock delay term behave the same way in both equations?

Candidate Model Response: The launch-clock delay term shifts the launch edge, not the capture edge, so its effect runs the opposite way from the capture term in each check. A later launch edge gives the data less time to reach the capture register, hurting setup, while for hold a later launch edge is what's needed for the new data to have already started its race, so it interacts with the check differently than a later capture edge does. The launch and capture terms each need their own sign and their own OCV derating direction, worked out from first principles for the specific check, rather than assumed from the other term's behavior.

Practical Example

On a path with a 2 ns clock period, a capture-clock delay of 150 ps appears in both the setup and hold required-time equations as a subtracted term. For setup, that 150 ps effectively gives the data 150 ps more time to arrive, moving a marginal path from -20 ps slack to +130 ps slack. For hold, the same 150 ps of capture-clock delay tightens the hold margin by 150 ps, moving a comfortable +200 ps hold slack down to +50 ps — the identical number, subtracted the same way in both equations, produces a better outcome for one check and a worse one for the other.

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