IntermediateQuestion 36 of 112

Why does a two-rail level shifter need at least eight scaling libraries?

From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide

Short Answer

A level shifter spans two power domains, so its timing depends on two independent rail voltages plus temperature. Covering all three dimensions on-grid needs 2 x 2 x 2 = 8 corner combinations, against 2 x 2 = 4 for an ordinary single-rail cell that only depends on one voltage and temperature.

Technical Reference DiagramWhy does a two-rail level shifter need at least eight scaling libraries?

Technical Explanation

The number of scaling libraries a cell needs is set by how many independent things its delay depends on, and a level shifter has one more dimension than an ordinary cell.

  • The single-rail baseline: a normal cell's timing depends on its one supply voltage and on temperature, so covering both endpoints of each dimension on-grid needs 2 (voltage) times 2 (temperature) = 4 libraries.
  • What's different about a level shifter: it connects two different power domains, so its delay is a function of both rail voltages independently, plus temperature โ€” a genuinely higher-dimensional characterization problem.
  • The resulting count: the on-grid corner set is the product across all three axes โ€” 2 for rail 1, times 2 for rail 2, times 2 for temperature โ€” giving 2 x 2 x 2 = 8 libraries.
  • Why you can't economize by assuming the rails move together: in a real multi-voltage design the two rails vary independently โ€” one domain can sit at nominal while the other is scaled down by DVFS (dynamic voltage and frequency scaling) โ€” so a library set that only covers the rails moving in lockstep leaves the mixed combinations uncharacterized.
  • Why those mixed combinations matter most: they are exactly the operating points a level shifter exists to handle โ€” one side high, one side low โ€” so skipping them defeats the point of characterizing the cell at all.
  • What happens with fewer than eight: the tool has no on-grid data for some legitimate rail-voltage pairs it will be asked to time, forcing interpolation or extrapolation across a gap the characterization never covered.

Common Mistake

The Trap: budgeting library characterization for a level shifter the same way as a single-rail cell, assuming the two rails scale together.

  • A characterization team reuses the 4-corner plan from ordinary cells, pairing the two rails' voltage moves as if they always change in lockstep.
  • The real DVFS use case, where one domain scales down while the other stays at nominal, has no on-grid library entry, so the tool must interpolate across an uncharacterized gap exactly at the corner where the level shifter's behavior is most nonlinear.

Follow-up Question & Model Response

If a design has three power domains meeting at a level shifter with two output rails and one shared reference, does the count change again?

Candidate Model Response: Yes โ€” the count scales with however many independent voltage-dependent terminals the cell actually has, not with a fixed "two-rail" assumption. A cell with two independently varying rails plus a third reference voltage that also moves independently would add another factor of 2, unless that third terminal is tied to one of the other two or held fixed by design. The general rule is 2 raised to the power of however many independent voltage dimensions the cell depends on, times 2 for temperature, so it's worth checking the cell's actual supply pin connections in the library before assuming a fixed library count.

Practical Example

A chip has a 1.0V always-on domain and a 0.6V-to-0.9V DVFS domain connected through a level shifter. The characterization plan covers rail 1 at {0.6V, 0.9V}, rail 2 at {0.9V, 1.0V}, and temperature at {-40C, 125C}, giving the full 2x2x2 = 8 library set. When the DVFS domain drops to 0.6V while the always-on domain stays at 1.0V, that exact 0.6V/1.0V/temperature combination has an on-grid library entry, so report_timing (PT) uses characterized data directly rather than interpolating between corners that never represented that mixed operating point.

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