ExpertQuestion 18 of 69

What are RC corners (Cmax/Cmin/RCmax/RCmin), and why might the worst corner differ between a short capacitance-dominated net and a long resistance-dominated net?

From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide

Short Answer

RC corners model the extremes of interconnect variation caused by manufacturing spread in wire width and spacing. Cmax pairs wider wires and tighter spacing (lower resistance, higher capacitance); Cmin pairs narrower wires and wider spacing (higher resistance, lower capacitance); RCmax and RCmin describe the analogous extremes when resistance, not capacitance, dominates delay. A short net's delay is driven mostly by capacitive loading, so Cmax tends to be its setup-worst corner; a long net's delay is driven mostly by resistive RC delay, so RCmax tends to be its setup-worst corner instead โ€” the same physical wire extremes stress different nets differently depending on which effect actually dominates their delay.

Technical Reference DiagramWhat are RC corners (Cmax/Cmin/RCmax/RCmin), and why might the worst corner differ between a short capacitance-dominated net and a long resistance-dominated net?

Technical Explanation

  • Wire capacitance and resistance both depend on the wire's physical geometry after manufacturing, which varies from the drawn (nominal) dimensions due to process spread in etching, deposition, and photolithography.
  • A wire etched wider than nominal, with less spacing to its neighbors, has more sidewall and parallel-plate capacitance to those neighbors, but lower resistance because more metal cross-section is available for current to flow through โ€” this combination is the Cmax corner, since capacitance is at its maximum.
  • The opposite combination โ€” narrower wire, more spacing โ€” gives lower capacitance but higher resistance, since less metal cross-section is available; this is the Cmin corner.
  • For a short net driving a simple capacitive load, the dominant delay term is roughly proportional to the total capacitance the driver has to charge or discharge, so the higher-capacitance Cmax corner tends to produce the longest delay, making it the setup-worst corner for that net; the lower-capacitance Cmin corner, with less to charge, tends to be fastest and is often the hold-worst corner instead.
  • For a long net, resistive RC delay (distributed resistance along the wire interacting with capacitance) becomes the dominant term rather than simple capacitive loading, and the corner that maximizes that RC product is not necessarily the same corner that maximizes capacitance alone โ€” RCmax specifically characterizes the corner combination (narrower wire, higher resistance, with capacitance treated according to which combination produces the worst RC delay product) that is worst for this resistance-dominated regime; RCmin is its counterpart for the fastest resistance-dominated case.
  • Because Cmax/Cmin optimizes purely for capacitance extremes while RCmax/RCmin optimizes for the RC delay product, a design with a mix of short, capacitance-dominated nets and long, resistance-dominated nets genuinely needs both corner pairs analyzed โ€” neither one alone bounds every net's worst case.
  • What breaks: signing off only against Cmax/Cmin on a design with long, resistance-heavy global routing (a wide bus or a long clock spine, for example) can miss the true worst-case delay those specific nets experience, since their delay is not primarily governed by the capacitance-only extreme.

Common Mistake

The Trap: assuming Cmax is universally "the worst-case RC corner" for every net in the design.

  • A net dominated by distributed wire resistance (long, thin routing) can see its true worst-case delay at RCmax, not Cmax, because Cmax specifically maximizes capacitance, not the RC delay product that dominates that net's actual behavior.
  • Skipping RCmax/RCmin extraction corners entirely because Cmax/Cmin are already being run assumes the two corner pairs are redundant, when they are actually characterizing different physical regimes and can each be uniquely worst for different subsets of the design's nets.

Follow-up Question & Model Response

"A long, thin clock spine net shows its worst setup slack at RCmax rather than Cmax in your signoff runs. Is that a red flag, or expected behavior โ€” and what would make you investigate further?"

Candidate Model Response: That is expected, not a red flag by itself โ€” a long, thin net is exactly the resistance-dominated case where RC delay, not raw capacitance, drives worst-case delay, so RCmax being its true worst corner is consistent with the physics. I would only investigate further if the gap between the RCmax and Cmax slack numbers on that net were unusually large compared to similarly-shaped nets elsewhere in the design, since that could indicate a specific extraction or routing issue on that particular net rather than the expected RCmax-versus-Cmax behavior for its geometry.

Practical Example

Worked case: a 50 micron short net driving a single register load has 30 fF of capacitance at Cmax versus 22 fF at Cmin, and negligible resistance either way โ€” Cmax gives its worst setup delay directly through the larger capacitive load. A 2000 micron clock spine net on the same design has resistance dominate: at RCmax its distributed RC delay is 180 ps, worse than the 140 ps it shows at Cmax, because RCmax's higher-resistance, thinner-wire combination stresses the resistive term the capacitance-only Cmax corner does not fully capture. Signing off the clock spine only against Cmax would have understated its true worst-case delay by 40 ps.

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