BeginnerQuestion 9 of 95

What is a setup check, and what is setup time?

From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide

By Tabish Iqbal, who has 9+ years of VLSI Physical Design experience

Short Answer

A setup check confirms that data launched on one clock edge arrives and settles at the capturing flip-flop's data pin before that flop's next active clock edge, with enough margin to spare. Setup time is that margin — the minimum stretch of time the data must sit stable right before the clock edge for the flop to capture it reliably.

Setup check: data arrival must land before the required deadline set by the next capturing clock edge minus setup time and uncertainty — Technical Reference DiagramWhat is a setup check, and what is setup time?

Technical Reference DiagramWhat is a setup check, and what is setup time?

Technical Explanation

Setup enforces the slowest a path is allowed to be, which makes it the check that limits how fast the clock can run.

What setup time protects against. Inside the flip-flop, the clock edge triggers an internal circuit that needs the data input to already be stable, so it can settle to the correct stored value without landing in an undefined in-between state.
The check in plain terms. Launch delay (clock tree plus clock-to-Q) plus the worst-case combinational delay must not exceed the deadline set by the next clock edge, minus the cell's setup time and uncertainty, plus any CRPR credit.
Setup slack is required time minus arrival time. A positive number means the path finished with margin to spare; a negative number is a violation the design cannot tape out with.
Setup is checked at the slow corner. The tool evaluates setup using the slowest realistic process, lowest voltage, and highest temperature, since that's when gate and wire delays are at their largest and the path is most likely to be late.

Common Mistake

The trap: trying to fix a setup violation by inserting extra delay buffers into the path.
The instinct comes from fixing hold violations the same way, where adding delay genuinely helps.
For setup, adding delay makes the data arrive later still, which only makes a negative slack more negative — the fix has to reduce delay (or move the deadline later), never add it.

Follow-up Question & Model Response

What are the actual physical-design levers for fixing a setup violation?

Candidate Model Response: Upsizing the driving cells reduces their gate delay by giving them more drive strength. Inserting a pipeline register splits one long combinational stretch into two shorter ones across an extra clock cycle. Reworking placement shortens the wires contributing to the delay. Swapping to a faster-switching cell (a lower-threshold-voltage variant) trims cell delay at the cost of some leakage power. And delaying the capture clock on purpose — useful skew — effectively pushes the deadline later for that specific path.

Practical Example

A multiply-accumulate path was reported with −120 ps of setup slack. Swapping its standard-threshold cells for faster low-threshold equivalents cut the combinational delay by 180 ps, turning the violation into +60 ps of positive slack without changing the logic or the clock.

Complete STA Handbook