BeginnerQuestion 10 of 95

What is a hold check, and what is hold time?

From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide

By Tabish Iqbal, who has 9+ years of VLSI Physical Design experience

Short Answer

A hold check confirms that data launched on a clock edge stays stable at the capturing flip-flop's data pin for a minimum stretch of time after that same clock edge. Hold time is that minimum stretch — the flop needs the data to hold still just long enough for its internal capture circuit to fully latch the value before anything new arrives.

Hold check: data must stay stable after the same clock edge for at least hold time, independent of clock period — Technical Reference DiagramWhat is a hold check, and what is hold time?

Technical Reference DiagramWhat is a hold check, and what is hold time?

Technical Explanation

Hold enforces the fastest a path is allowed to be, which is the opposite direction from setup.

What hold time protects against. Right after the clock edge, the flop is still finishing the internal process of capturing the old data. If new data races in and changes the input too soon, it can corrupt the value being captured — this is a race condition, not a speed limit.
The check in plain terms. Launch delay plus the fastest-case combinational delay must not be smaller than the capture clock's delay plus the cell's hold time and uncertainty, minus any CRPR credit.
Hold slack is arrival time minus required time, calculated at the fast corner rather than the slow one used for setup.
The clock period never appears in the hold equation. Hold compares the same clock edge to itself, not to the next cycle — which is exactly why a hold violation cannot be fixed by simply slowing down the clock.
Hold is checked at the fast corner. The tool evaluates hold using the fastest realistic process, highest voltage, and lowest temperature, since that's when delays are smallest and a race condition is most likely.

Common Mistake

The trap: believing a hold violation found in the lab can be worked around by running the chip at a slower clock frequency.
It's an understandable guess, since slowing the clock fixes almost every other timing problem people encounter.
Hold has nothing to do with the clock period — silicon with a genuine hold violation will fail at any frequency, even one cycle per second, because the race happens within a single clock edge, not across a cycle boundary.

Follow-up Question & Model Response

How do physical-design tools fix hold violations automatically without breaking setup on the same path?

Candidate Model Response: They insert non-inverting delay buffers, or swap in higher-threshold-voltage cells, specifically on paths that already have comfortable positive setup slack. Adding delay there slows the path down just enough to fix the hold race, and because that path had setup margin to spare, the added delay doesn't push it into a setup violation. The tool avoids touching paths with tight setup margin for exactly this reason.

Practical Example

In a shift register where one flop's Q pin connected directly to the next flop's D pin with essentially zero combinational delay, clock skew alone produced a −45 ps hold violation at the fast, cold corner. Inserting a small delay buffer added about 70 ps of extra minimum delay to that path, clearing the violation without affecting the register's setup timing at all.

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