Level 1: Foundations

Beginner STA Interview Questions

Build the vocabulary and timing-path mental model needed to read constraints and reports accurately.

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What to practise at this level

Build the vocabulary and timing-path mental model needed to read constraints and reports accurately.

01 What is Static Timing Analysis (STA), and why do we need it?Beginner: Static timing analysis (STA) checks every timing path in a chip design without simulating any data. It walks each path once, adds up the worst-case delays, and compares that total against the clock period. The tool does this for every path at once, so it can prove the whole chip meets its setup and hold requirements instead of just sampling a few cases.
02 Why can't circuit simulation alone verify that a chip meets timing?Beginner: Circuit simulation only tests the exact input sequences a testbench happens to apply. A modern chip has far too many possible internal states for any testbench to trigger the one combination that produces the slowest, worst-case path. Static timing analysis avoids this problem entirely by checking delay algebraically instead of by simulating data.
03 What is a timing path?Beginner: A timing path is the route a signal takes from one fixed point to another: a startpoint where data is launched, through combinational logic, to an endpoint where data is captured. Every delay and slack number the tool reports is calculated for one specific timing path.
04 What are startpoints and endpoints of a timing path?Beginner: A startpoint is where the tool considers data to be launched — a flip-flop's clock pin or a primary input port. An endpoint is where the tool checks that data arrived correctly — a flip-flop's data pin or a primary output port. These are the only object types the tool will accept as path boundaries.
05 What are the four categories of timing paths (reg2reg, in2reg, reg2out, in2out)?Beginner: Every timing path in a design falls into one of four shapes, named for its startpoint and endpoint: register-to-register (reg2reg), input-to-register (in2reg), register-to-output (reg2out), and input-to-output (in2out). Each shape is constrained by a different SDC command, because each one crosses the chip boundary differently.
06 How do you define a clock in SDC, and what does the create_clock command do?Beginner: `create_clock` (SDC) is the command that tells the tool a clock exists: its period, where it enters the design, and the shape of its waveform. Without it, the tool has no reference edge to launch or capture data against, so no synchronous timing check can happen at all.
07 What is data arrival time?Beginner: Data arrival time is the total time the tool calculates from the launch clock edge (time zero) until the data signal actually reaches and switches at the capturing flip-flop's data pin. It's the sum of every delay along the path — clock tree, the launching flop itself, and the logic in between.
08 What is data required time?Beginner: Data required time is the deadline the tool computes for a path: the latest moment data may arrive (for a setup check) or the earliest moment data may safely change (for a hold check) at the capturing flip-flop. It comes from the clock period, the capturing clock's own delay, and the cell's own setup or hold requirement.
09 What is a setup check, and what is setup time?Beginner: A setup check confirms that data launched on one clock edge arrives and settles at the capturing flip-flop's data pin before that flop's next active clock edge, with enough margin to spare. Setup time is that margin — the minimum stretch of time the data must sit stable right before the clock edge for the flop to capture it reliably.
10 What is a hold check, and what is hold time?Beginner: A hold check confirms that data launched on a clock edge stays stable at the capturing flip-flop's data pin for a minimum stretch of time after that same clock edge. Hold time is that minimum stretch — the flop needs the data to hold still just long enough for its internal capture circuit to fully latch the value before anything new arrives.
11 What is slack?Beginner: Slack is the tool's margin number for a path: how much room there was between when data was required and when it actually arrived. For setup, slack is required time minus arrival time. For hold, it's the other way around — arrival time minus required time.
12 What do positive slack and negative slack mean?Beginner: Positive slack means a path met its timing requirement with margin left over — the design is safe on that check. Negative slack means the path missed its requirement, which is a real timing violation that will cause incorrect behavior in silicon unless it gets fixed before tapeout.
13 What are launch and capture flip-flops?Beginner: The launch flip-flop is the one whose clock edge sends new data into the path being timed. The capture flip-flop is the one whose clock edge samples and stores whatever arrives. Every register-to-register path the tool reports has exactly one launch flop and one capture flop, even though a single flop often plays both roles for different paths.
14 What does set_input_delay do?Beginner: `set_input_delay` (SDC) tells the tool how much of the clock period was already used up before a signal reached one of the chip's input ports — time spent on the board, in the driving chip's own delay, and in wire flight time. It doesn't add any actual delay inside the chip; it's purely information the tool uses to compute correct arrival times for paths starting at that port.
15 What does set_output_delay do?Beginner: `set_output_delay` (SDC) tells the tool how much time must be left over, after a signal leaves the chip's output port, for the board and the receiving device's own setup or hold needs. Like `set_input_delay`, it's a timing assertion the tool uses for its math, not a delay it physically inserts.
16 What is clock uncertainty?Beginner: Clock uncertainty is a margin the tool builds into every setup and hold check to cover clock jitter, skew the model can't fully predict, and other small clock imperfections. It's subtracted from the setup deadline (making it stricter) and added to the hold deadline (also making it stricter) through `set_clock_uncertainty` (SDC).
17 What is clock latency, and what's the difference between source latency and network latency?Beginner: Clock latency is the total time it takes the clock signal to travel from its true origin to a specific flip-flop's clock pin. The tool splits that total into two pieces: source latency, the delay before the clock even reaches the design's defined clock point, and network latency, the delay from that point through the on-chip clock tree to the flop.
18 What is clock skew?Beginner: Clock skew is the difference in arrival time between the clock edge reaching the capture flip-flop and the clock edge reaching the launch flip-flop, on the same path. It shifts how much time the data path effectively has — positive skew gives setup more room but takes room away from hold, and negative skew does the reverse.
19 What is combinational (logic) delay in a timing path?Beginner: Combinational logic delay is the total time added by ordinary logic gates — AND, OR, XOR, multiplexers, inverters — sitting between the launch flop's output and the capture flop's input on a timing path. It's usually the single largest, and most controllable, piece of a path's total delay.
20 What is cell delay?Beginner: Cell delay is the time it takes a single standard cell's output to switch after its input switches, measured between the same reference points (typically each pin's 50% voltage crossing). The tool looks this number up in the cell's own Liberty library data rather than calculating it from first principles.
21 What is net delay (interconnect delay)?Beginner: Net delay (also called interconnect delay) is the time a signal takes to travel along the metal wiring between two pins, once it leaves the driving cell. It comes from the wire's own resistance and capacitance (RC), not from any transistor switching.
22 How do you read a basic timing report from report_timing?Beginner: A `report_timing` (PT) report has four parts read top to bottom: a header naming the start and end of the path, a data-arrival section tracing the signal's delay pin by pin, a data-required section computing the deadline, and a slack line at the bottom showing whether the path passed.
23 What is an SDC file, and what are 'basic timing constraints'?Beginner: An SDC (Synopsys Design Constraints) file is a plain-text script that tells the tool what timing the design is supposed to meet — its clocks, its I/O timing, and any exceptions — before synthesis, place-and-route, or STA can check anything against it.
24 What is a setup violation, and what does it mean physically?Beginner: A setup violation means data arrived at a flip-flop's input too close to the clock edge — later than the setup time the flop needs to latch it reliably. It signals that the design is too slow for the clock period being tested, not that the chip is necessarily broken.
25 What is a hold violation, and what does it mean physically?Beginner: A hold violation means new data raced through the logic and reached a flip-flop's input before the flop had finished safely latching the previous value, corrupting that stored bit. Unlike a setup violation, a hold violation cannot be fixed by running the clock slower.
26 What is slew (transition time), and why does it matter?Beginner: Slew, also called transition time, is how long a signal takes to swing from a low logic level to a high one, or back again. A slower slew adds extra delay to every gate downstream, wastes power, and makes a wire more vulnerable to noise from its neighbors.
27 What is a standard cell timing library (Liberty), and what does it contain?Beginner: A Liberty (.lib) library is a text file that describes exactly how every standard cell in a technology behaves — its delay, its output slew, its input pin capacitance, and its power draw — measured across the range of input slews and output loads the cell might see.
28 What is NLDM (Non-Linear Delay Model)?Beginner: NLDM (Non-Linear Delay Model) is the classic way a Liberty library stores cell delay — a two-dimensional lookup table indexed by input slew and output load, with the tool interpolating between the table's measured points for any value in between.
29 What are PVT corners, and why does timing change across them?Beginner: PVT corners are combinations of Process, Voltage, and Temperature that real chips will actually experience across manufacturing spread and normal operating conditions. Timing shifts noticeably across them because the physical speed of a transistor depends on all three.
30 What is the difference between an ideal clock and a propagated clock?Beginner: An ideal clock reaches every register at the same instant, with no physical clock tree modeled yet. A propagated clock is traced through the design's real clock buffers and wires, so it carries the true insertion delay and skew that physical clock tree synthesis actually produced.
31 What is WNS (Worst Negative Slack)?Beginner: Worst Negative Slack (WNS) is the most negative slack value found across every endpoint in a design or path group. It tells you the single most timing-critical path in the design, and how far the design is from meeting its target clock frequency.
32 What is TNS (Total Negative Slack)?Beginner: Total Negative Slack (TNS) is the sum of every violating endpoint's slack across the design, added together as negative numbers. It measures how widespread timing failure is, in a way that a single worst-path number like WNS cannot.
33 What is a generated clock?Beginner: A generated clock is a clock produced inside the design itself — by a divider, a multiplexer, or a clock-gating cell — rather than arriving from an external pin. It is declared with `create_generated_clock` (SDC) so the tool keeps it tied to the timing of the master clock it comes from.
34 What is a false path?Beginner: A false path is a timing exception, declared with `set_false_path` (SDC), that tells the tool to stop checking both setup and hold on a path because that path can never actually be exercised in real functional operation.
35 What is a multicycle path?Beginner: A multicycle path is a timing exception, declared with `set_multicycle_path` (SDC), that tells the tool a path is deliberately allowed more than one clock cycle to complete, instead of the default single-cycle deadline every path is checked against.
36 What does the check_timing command do, and why should you run it before trusting any report?Beginner: The `check_timing` (PT) command audits the loaded design and constraints for setup problems that would make slack reports meaningless — unclocked registers, unconstrained ports, and combinational loops — before you rely on any slack number it produces.
37 What are parasitics, and what is SPEF?Beginner: Parasitics are the resistance and capacitance a routed wire has simply by existing as metal near other metal and near the substrate. SPEF (Standard Parasitic Exchange Format) is the file format used to carry those extracted values from the layout tool into the STA tool.
38 What is the difference between pre-layout and post-layout STA?Beginner: Pre-layout STA runs on the synthesized netlist with ideal clocks and estimated wire delay, before physical placement exists. Post-layout STA runs on the actual routed design with propagated clocks and real extracted wire parasitics, and is the version that counts for signoff.
39 What are the major input files STA needs to run (netlist, library, SDC, parasitics)?Beginner: STA needs four files to run: a gate-level netlist describing what is connected to what, Liberty timing libraries describing how each cell behaves, an SDC file stating the timing intent, and — for post-layout accuracy — a SPEF file with extracted wire parasitics.
40 What is timing signoff?Beginner: Timing signoff is the final checkpoint where a design must show zero setup and hold violations, clean design-rule checks, and full path coverage across every required corner, before the layout is released for manufacturing.
41 What is the critical path, and how does it differ from a timing violation?Beginner: The critical path is the path with the least slack in the whole design, whether that slack is positive or negative. It is not automatically a timing violation — a design with a healthy, all-positive-slack timing report still has a critical path, it is just the one closest to failing.
42 What is a timing arc, and why do rising and falling edges have different delays?Beginner: A timing arc is the delay from one specific input transition on a cell to one specific output transition — for example, input rising to output falling. A single gate has several arcs, and the tool tracks each one separately because the delay is not the same for every combination.
43 What is the difference between a setup/hold check and a design rule check like max transition?Beginner: A setup or hold check compares two clock-relative times on a path and produces slack — a value that can be positive or negative. A design rule check (DRC) like max transition compares a single measured value against a fixed library or user limit, with no clock relationship involved at all.
44 What does it mean for a timing path to be unconstrained?Beginner: An unconstrained path is one the tool can trace electrically but has no timing requirement attached to — no clock relationship or `set_input_delay`/`set_output_delay` (SDC) tells it what "on time" means. The tool will not report a slack number for it at all, good or bad.
45 Why can multiple paths end at the same flip-flop, and which one does STA report?Beginner: A flip-flop's data input is usually fed by several different upstream logic paths that converge through a mux or a gate, so more than one path can share the same endpoint. The tool reports the one with the worst slack for that endpoint, not every path that reaches it.
46 What is a virtual clock, and why would you create one that doesn't drive any pin?Beginner: A virtual clock is a clock the designer defines with `create_clock` (SDC) but never attaches to any real port or pin in the design. It exists only so the tool has a timing reference for signals that talk to an off-chip device on a clock the chip itself does not generate.
47 How do you model a clock with an uneven duty cycle using the waveform option?Beginner: By default, `create_clock -period` (SDC) assumes a perfectly even 50% duty cycle clock. To model a clock that is high or low for a different fraction of its period, add the `-waveform` option and list the exact rise and fall edge times yourself.
48 What happens in PrimeTime if you forget to define a clock on a clock port?Beginner: Without a `create_clock` (SDC) statement, the tool has no reason to treat that port as a clock at all — it times signals through it as ordinary combinational logic, and every flip-flop it should be clocking shows up as having no clock.
49 What is a clock domain, and why does a chip usually have more than one?Beginner: A clock domain is the group of flip-flops and logic that all get their clock from the same defined clock, directly or through a generated clock derived from it. Most chips have several domains because different parts of the design genuinely need to run at different speeds.
50 How many clocks can one SDC file define, and do they need the same period?Beginner: An SDC file can define as many clocks as the design has clock sources or generated-clock points — there is no fixed limit. Each clock gets its own independent period, waveform, and name, so none of them are required to match any other clock's period.
51 What does set_clock_transition do, and how is it different from set_clock_uncertainty?Beginner: `set_clock_transition` (SDC) tells the tool how slow the clock edge itself is — its rise or fall time — when the clock network is still ideal and has no real buffers to measure that from. `set_clock_uncertainty` (SDC) is a completely different number: extra margin subtracted from the setup or hold check to cover skew and jitter.
52 What is clock sense, and what does it mean for a clock to trigger on the falling edge?Beginner: Clock sense describes which edge direction of a clock signal a flip-flop actually reacts to — rising-edge-triggered or falling-edge-triggered. Most designs use rising-edge flops, but a design can deliberately use falling-edge flops, often to build a double-data-rate interface or to relax a tight setup path.
53 How do you tell PrimeTime that two clocks are asynchronous with set_clock_groups?Beginner: `set_clock_groups -asynchronous` (SDC) tells the tool that the listed groups of clocks have no fixed timing relationship to each other at all, so it should not build a setup or hold check across any path between them. Paths within each group are still checked normally.
54 What time unit does an SDC file use, and why does getting it wrong break every constraint?Beginner: SDC commands take plain numbers with no unit attached, and the tool interprets every one of them in whatever time unit the design's own technology library or `set_units` (SDC) statement declares — nanoseconds is the most common default. Every number in the file only means anything relative to that one setting.
55 Why does create_clock need a period value, and what happens if you pick the wrong one?Beginner: The period is what lets the tool compute a required time at all — every setup check measures arrival time against one clock cycle length, so `create_clock` (SDC) cannot build a usable clock without it. Picking a period looser than the real target hides real violations; picking one tighter wastes design effort chasing margin nobody needed.
56 What is set_case_analysis, and when would you tie a pin to a fixed value?Beginner: `set_case_analysis` (SDC) tells the tool to treat a pin as permanently stuck at a fixed logic value — 0 or 1 — for the whole analysis, instead of a signal that can still switch. Designers use it for pins that really are fixed in the mode being analyzed, such as a tied-off test or configuration input.
57 Why would a designer mark a path as a false path instead of just leaving it unconstrained?Beginner: Leaving a path unconstrained means the tool never checks it at all and cannot tell an intentionally irrelevant path from a genuine constraint gap. Marking it a false path with `set_false_path` (SDC) is a deliberate, documented statement that the path was checked and judged not to need timing at all.
58 What is a half-cycle path, and why can it look like a timing violation when it isn't?Beginner: A half-cycle path is one where the launching and capturing flip-flops are triggered by opposite edges of the same clock, so data only has half a clock period, not a full one, to get there. It is not automatically a violation — it just needs to be measured against the correct, shorter required time.
59 What is set_disable_timing, and when would you turn off an entire timing arc?Beginner: `set_disable_timing` (SDC) removes one specific timing arc — a delay from one pin to another inside a cell or between two points — from analysis entirely, as if that internal connection did not exist. It is used when a real electrical path exists but is never functionally active in the mode being timed.
60 What is set_max_delay and set_min_delay, and how do they differ from set_false_path?Beginner: `set_max_delay` and `set_min_delay` (SDC) give a path an explicit time budget in nanoseconds directly, instead of deriving one from a clock relationship. `set_false_path` (SDC) removes a path from checking entirely; these two commands keep the path checked, just against a number the designer states outright.
61 Why does marking a path false when it actually toggles cause a silicon bug?Beginner: `set_false_path` (SDC) tells the tool to stop checking a path's delay completely — it does not stop the real hardware from switching. If that path genuinely does carry a changing signal during functional operation, its real delay is never verified, and a slow path can fail silently in silicon while every report stays clean.
62 What does -through, -from, and -to mean when writing a timing exception?Beginner: `-from` and `-to` name a path's startpoint and endpoint directly — a clock, a register, or a port. `-through` instead names one or more intermediate points the path must pass through on its way there, letting the designer target one specific route among several that share the same start and end.
63 What is derating, and why does PrimeTime multiply delays by a margin?Beginner: Derating is the practice of scaling a calculated delay up or down by a fixed factor to account for the fact that two identical-looking gates on the same chip do not switch at exactly the same speed. PrimeTime applies a derate factor with `set_timing_derate` (SDC) so setup and hold checks assume a small, safe amount of extra variation instead of trusting one single delay number for every instance. It is the tool's way of modeling on-chip variation without having to know the exact speed of every gate up front.
64 What is the difference between an early derate and a late derate?Beginner: A late derate scales a delay up, making a path look slower than the "typical" number calculated it to be, and PrimeTime applies it wherever running late is the dangerous direction. An early derate scales a delay down, making a path look faster, and the tool applies it wherever running early is the dangerous direction. Which paths get which derate flips depending on whether the tool is checking setup or hold.
65 Why does PrimeTime apply different derate values to cell delay and net delay?Beginner: Cell delay comes from a transistor's switching speed, which depends on process parameters like threshold voltage that vary meaningfully from one physical location on the die to another. Net delay comes mostly from wire resistance and capacitance, set by the metal stack's geometry, which varies far less across a die than transistor speed does. Because the two delay types come from different physical sources with different amounts of variation, PrimeTime lets you set separate derate factors for each with `-cell_delay` and `-net_delay` (SDC) instead of forcing one number to cover both.
66 What is a single flat OCV derate, and why isn't it enough for modern designs?Beginner: A flat OCV derate applies the same percentage margin to every cell and every net in the design, regardless of how many logic stages a path crosses or how far apart the launch and capture clock paths are. It is simple to set up with one `set_timing_derate` (SDC) command, but it treats a two-stage path and a forty-stage path as equally risky, which is not how real variation behaves. As designs grow, that flat number either wastes margin on short paths or under-covers long ones.
67 What is statistical on-chip variation, and how does POCV differ from a flat derate percentage?Beginner: Parametric on-chip variation, POCV, models each cell's delay as a range described by a mean value and a standard deviation, or sigma, instead of one worst-case number scaled by a fixed percentage. PrimeTime reads this mean-and-sigma data from the Liberty library's variation tables, sometimes called LVF data, and combines it statistically across a path rather than assuming every stage varies by the exact same fixed amount. That gives a derate that automatically adapts to how many stages a path has and how much each individual arc actually varies, instead of relying on one guessed percentage for the whole design.
68 What is clock reconvergence, and why does it matter for a hold check?Beginner: Clock reconvergence happens when the launch and capture paths of a timing check share part of the same physical clock tree before splitting off to different flip-flops. Because that shared portion is the exact same silicon for both paths, on-chip variation applied to it should cancel out instead of being counted twice, once as an increase on one side and a decrease on the other. PrimeTime's clock reconvergence pessimism removal, CRPR, finds that shared portion and removes the extra, unrealistic pessimism it would otherwise add, which matters most for hold checks because hold margins are already small.
69 Why do hold violations get worse as a chip moves to a smaller process node?Beginner: Hold checks care about the smallest possible delay difference between a launch path and a capture path, and shrinking transistor and wire geometry increases the percentage of random, uncontrollable variation in that smallest delay. A smaller node also means less absolute delay margin to begin with, because gates and short wires are faster, so the same picoseconds of variation eat up a much larger share of the available window. The result is that hold violations become more common and harder to fix even though the design intent has not changed.
70 What is signal integrity, and why can a quiet wire still glitch?Beginner: Signal integrity, often shortened to SI, covers what happens when a wire's voltage is disturbed by something other than its own driver, most commonly capacitive coupling from a switching neighbor. A wire that is not supposed to change at all, a quiet or static net, can still see a temporary voltage bump purely because a neighbor switched and coupled some of its energy across. PrimeTime's SI analysis checks for this alongside ordinary delay calculation, because the coupling can either slow a signal down or create a glitch large enough to be misread as a real logic transition.
71 What is the difference between an aggressor net and a victim net in crosstalk analysis?Beginner: A victim net is the wire PrimeTime is currently checking for a crosstalk effect, either a delay change or a noise glitch. An aggressor net is any neighboring wire, close enough to share meaningful coupling capacitance with the victim, whose own switching can push charge onto the victim and disturb it. The same physical wire can be a victim in one check and an aggressor in another, since the roles describe which net is being analyzed, not a fixed property of the wire itself.
72 What is coupling capacitance, and why does a neighbor's switching affect your delay?Beginner: Coupling capacitance is the capacitance that exists between two nets that run near each other on the chip, not between a net and the ground plane. Because that capacitance links the two wires electrically, a voltage change on one wire pushes some current through it onto the other, changing how quickly the second wire's own driver can charge or discharge its load. That is why a neighboring wire's switching can measurably speed up or slow down a signal's delay, an effect PrimeTime reports separately as crosstalk delay.
73 Why does STA need annotated parasitics instead of just a wire load model?Beginner: A wire load model estimates a wire's resistance and capacitance from statistics, an average length for a given fanout, before the design has real placement or routing. Annotated parasitics come from actually extracting the resistance and capacitance of the wires the tool physically routed, captured in a SPEF file, so they reflect the real length, shape, and neighbors of every specific wire. Once real layout exists, using annotated parasitics instead of a statistical estimate is what lets STA correlate with how the chip will actually behave.
74 What is an extraction corner, and why does signoff check RCmax and RCmin separately?Beginner: An extraction corner describes an assumption about how wide, thick, and closely spaced the manufactured metal wires actually turn out to be, since real fabrication varies within a controlled range around its target geometry. RCmax models the resistance-and-capacitance combination that makes wires act slowest for a given check, and RCmin models the combination that makes them act fastest, and signoff checks both because a wire varying toward one extreme is not guaranteed to vary the same way as one varying toward the other. This is separate from a PVT timing corner, which covers process, voltage, and temperature variation in transistors, not wires.
75 What is the difference between an NLDM lookup table and a CCS current-source model?Beginner: NLDM, non-linear delay model, describes a cell's delay and output transition as a lookup table indexed by input transition time and output load capacitance, giving a single number for each combination. CCS, composite current source, instead describes the cell's actual output current over time, letting the tool calculate delay more accurately when the load is not a simple capacitor, such as when crosstalk or a resistive interconnect is involved. Both come from the same Liberty library file format, but CCS carries more detailed information at the cost of a larger library and more calculation.
76 What is a timing mode in multi-mode multi-corner analysis?Beginner: A timing mode describes one functional operating condition of the chip, such as normal function, test/scan mode, or a low-power state, each of which can activate different clocks, different enabled paths, and different constraints. The same physical chip needs to meet timing in every mode it can actually be placed into, not just the one a design team thinks of as "normal," because a path that is safely disabled in one mode might be fully active in another. Multi-mode analysis runs the design through each mode's own SDC constraints to check timing holds up in every one of them.
77 What is a timing corner, and how is it different from a timing mode?Beginner: A timing corner describes a set of physical operating conditions the silicon might actually see, such as process variation, supply voltage, and temperature, often shortened to PVT. A timing mode, by contrast, describes a functional operating state the design's logic is in, such as scan test or a low-power state, and is about which paths and constraints are active rather than how fast the silicon physically runs. A full signoff scenario needs both: which mode the logic is in, and which corner's physical conditions apply for that check.
78 What is a scenario, and why does signoff run so many of them?Beginner: A scenario is one specific combination of a timing mode and a timing corner, analyzed together as a single, self-contained timing run with its own constraints and its own PVT or RC assumptions. Signoff needs many scenarios because a chip has to work correctly in every mode it can be placed into, under every corner condition the silicon might experience, and a violation hiding in just one untested combination is still a real silicon risk. Running many scenarios is how a design team gets confidence that no single mode-corner combination was left unchecked.
79 Why can't a single corner catch every timing problem in a modern chip?Beginner: Different timing checks are stressed by opposite physical conditions: setup checks get worse when the silicon runs slow, and hold checks get worse when it runs fast, so no single PVT corner is the worst case for both at once. A chip also has to work across its full specified range of voltage, temperature, and manufacturing outcome, not just one assumed condition, so checking only one corner leaves the rest of that range completely unverified. This is why signoff always runs multiple corners rather than trying to find one corner that represents every risk.
80 What is hierarchical timing analysis, and why analyze a block on its own?Beginner: Hierarchical timing analysis breaks a large design into smaller blocks and times each one somewhat independently, using a simplified model for how each block connects to the rest of the chip instead of loading the entire flat netlist in one run. Analyzing a block on its own lets a team get fast timing feedback and sign it off before the whole chip's netlist even exists in one piece, and it keeps the top-level run from becoming too large to manage. This matters most on large SoCs where a single flat run across the whole design would be too slow or too large to iterate on.
81 What is an extracted timing model, ETM, in plain terms?Beginner: An extracted timing model, ETM, is a simplified stand-in for a block's timing behavior, built by summarizing how each input pin affects each output pin, without keeping any of the internal gates that produced that behavior. It captures the delays and internal setup/hold checks the top-level design needs at the block's boundary, in a much smaller file than the block's full netlist and library data would require. Using an ETM instead of the full block lets a top-level run treat a large, complex block like a single, fast-to-load timing element.
82 What is timing budgeting, and why does each block get its own slack target?Beginner: Timing budgeting takes the total time available for a path crossing multiple blocks, one clock period, and divides it into smaller allowances for each block and each piece of interconnect the path passes through. Each block gets its own slack target because block teams typically work somewhat independently and in parallel, and giving each one a clear number to hit lets them close timing without needing the full top-level netlist available yet. Without budgeting, a multi-block path has no way to tell an individual block team whether their piece is the one using too much of the shared time.
83 What is the difference between report_timing and report_constraint in PrimeTime?Beginner: `report_timing` (PT) prints one path in full detail — every pin, every incremental delay, down to a single slack number. `report_constraint` (PT) instead scans the whole design and prints a summary: how many endpoints pass, how many fail, and by how much, for every check type at once. You reach for `report_timing` once you already know which path you care about, and for `report_constraint` when you still need to find out what is broken.
84 What do MET and VIOLATED mean in a PrimeTime constraint report?Beginner: MET and VIOLATED are the pass/fail labels `report_constraint` (PT) prints next to every checked endpoint. MET means the slack at that endpoint is zero or positive — the check passed with no margin problem. VIOLATED means the slack is negative, so the endpoint is failing that check and needs a fix or a legitimate exception.
85 What does report_analysis_coverage check that a slack report alone does not?Beginner: `report_analysis_coverage` (PT) reports what fraction of the design's paths and endpoints were actually included in the timing run, broken down by exception type and clock group. A design can show a completely clean `report_constraint` (PT) result and still hide real risk if large parts of it were excluded, disabled, or never constrained in the first place.
86 What does report_bottleneck do, and how is it different from checking one path at a time?Beginner: `report_bottleneck` (PT) ranks the individual cells and nets that show up most often across every failing path in the design, instead of listing the failing paths themselves. A single slow buffer or an overloaded net can sit on hundreds of different failing paths at once, and fixing that one cell clears all of them together.
87 What does report_delay_calculation show you that report_timing does not?Beginner: `report_timing` (PT) shows you the final delay number for each pin along a path. `report_delay_calculation` (PT) shows the underlying math behind one specific delay: the drive strength, the load it is driving, the slew it produces, and which library model or SPEF entry the tool used to compute it. You reach for it when a single delay number looks wrong and you need to see what produced it, not just that it exists.
88 What is the difference between the incremental and cumulative delay columns in a timing report?Beginner: The incremental delay column shows how much time one single stage — one cell or one net — adds by itself. The cumulative delay column, printed right next to it, is the running total of every incremental delay so far, from the path's startpoint up to that pin. The final cumulative value at the endpoint is the arrival time used in the slack calculation.
89 What is get_timing_paths, and why would you use it instead of report_timing?Beginner: `get_timing_paths` (PT) returns a Tcl collection of path objects that a script can loop over, filter, or measure, instead of printing a formatted report to the screen. `report_timing` (PT) is built for a person to read; `get_timing_paths` is built for a script to process, which matters once you need to check hundreds of paths automatically rather than read them one at a time.
90 What is an ECO, and when do you fix timing in PrimeTime instead of redoing place-and-route?Beginner: An ECO — engineering change order — is a small, targeted set of netlist changes made late in the flow to fix specific violations, instead of rerunning the full place-and-route flow. A designer reaches for PrimeTime's ECO commands when only a handful of cells need resizing or a few buffers need inserting, because a full re-implementation would cost far more schedule time than the violations are worth.
91 What is a DRC violation in timing signoff, and how is it different from a setup or hold violation?Beginner: A DRC (design rule constraint) violation happens when a signal's own physical limit is broken — its transition time is too slow, or its driven capacitance too high — regardless of any clock relationship. A setup or hold violation is always about a signal arriving too late or too early against a specific clock edge. A path can pass every setup and hold check and still fail a DRC limit, and vice versa.
92 What does write_changes do at the end of a PrimeTime ECO session?Beginner: `write_changes` (PT) takes every edit an ECO command like `fix_eco_timing` (PT) made inside PrimeTime's model and writes it out as a script of concrete netlist edits — cell resizes, buffer insertions, connections — that another tool can apply. Without this step, the ECO exists only inside PrimeTime's own view of the design and never reaches the real netlist or the physical layout.
93 Why does fixing a hold violation use different methods than fixing a setup violation?Beginner: A setup fix has to make a path faster, so `fix_eco_timing -type setup` (PT) uses cell sizing alone to shrink data-path delay. A hold fix has to make a path slower, so `fix_eco_timing -type hold` (PT) uses both sizing and buffer insertion to add delay back in. The two violations need opposite changes to the same path, which is why the tool treats them as separate fixing types, not one generic "fix timing" command.
94 Why must an ECO fix be re-verified with a full STA run before signoff, instead of trusting the ECO tool's own report?Beginner: `fix_eco_timing` (PT) reports the violations it believes it fixed based on PrimeTime's own timing model at the moment it ran, but that model can go stale the instant the physical tool actually places, routes, and legalizes the new cells. A full STA re-run, with freshly extracted parasitics, is the only way to confirm the fix holds in the design as it will actually be built, not as PrimeTime estimated it.
95 What is the difference between a timing ECO and a functional ECO?Beginner: A timing ECO only changes non-functional properties of the netlist — cell sizes, buffer insertion, wire routing — to fix a timing or design-rule violation without changing what the chip logically does. A functional ECO changes the logic itself: a gate is added, removed, or rewired to fix a real behavioral bug. The two are handled very differently late in a project, because a functional change can ripple through verification in ways a timing-only change cannot.

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