What is a timing path?
From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
A timing path is the route a signal takes from one fixed point to another: a startpoint where data is launched, through combinational logic, to an endpoint where data is captured. Every delay and slack number the tool reports is calculated for one specific timing path.
Technical Explanation
The tool builds its entire report around this one unit: the path.
- Startpoints launch data. A path always begins at a clock pin of a flip-flop (data leaves right after the clock edge) or at a primary input port (data arrives from outside the chip).
- The combinational cloud does the work. Between the startpoint and endpoint sits ordinary logic — AND gates, multiplexers, inverters — plus the wires connecting them. Each one adds delay.
- Endpoints capture data. A path always ends at a data input pin of a flip-flop (where the value gets stored) or at a primary output port (where it leaves the chip).
- The total is just addition. Path delay = clock-to-Q delay of the launching flop, plus every gate delay along the way, plus every wire delay along the way. The tool adds these up once per path to get the arrival time.
- A gate's own output pin is never a boundary. Only sequential pins and chip ports qualify as startpoints or endpoints — an internal AND-gate output is just a point inside the cloud, not a path edge.
Common Mistake
- The trap: pointing at an internal gate's output pin and calling it a startpoint or endpoint.
- It's an easy assumption, since a gate output does mark where one signal stage ends and the next begins.
- But the tool only recognizes sequential clock/data pins and chip ports as boundaries — trying to reference a plain gate pin as a path edge in a timing exception simply won't match anything.
Follow-up Question & Model Response
Can the same element be both a startpoint and an endpoint within the same design?
Candidate Model Response: Yes, a transparent latch can play both roles. While a latch is open (transparent), data can pass straight through it in the same cycle — a behavior called time borrowing. Looked at from the upstream logic's side, the latch is the endpoint that captures that stage's result. Looked at from the downstream logic's side, the same latch is the startpoint that just re-launched the data onward. A flip-flop can't do this in one cycle, but a latch can, because it doesn't fully close the moment the clock edge happens.
Practical Example
In a 64-bit ALU datapath, the tool identifies roughly 25,000 separate register-to-register paths between the pipeline's operand registers and its accumulator register. It evaluates every one of those 25,000 paths in the same run, then reports back just the one with the least slack — the critical path — as the number to watch first.
Complete STA Handbook
Master Signoff-Ready Static Timing Analysis
Get the complete 10-chapter STA handbook covering setup/hold margins, clock modeling, OCV/POCV, crosstalk noise, and PrimeTime closure.
Offline PDF Bundle
Want all 1109 questions offline?
Get the complete 4-book PDF bundle (PnR, STA, MMMC, Low Power) with a clickable table of contents - no ads, no internet needed.
Continue practising