BeginnerQuestion 2 of 95

Why can't circuit simulation alone verify that a chip meets timing?

From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide

By Tabish Iqbal, who has 9+ years of VLSI Physical Design experience

Short Answer

Circuit simulation only tests the exact input sequences a testbench happens to apply. A modern chip has far too many possible internal states for any testbench to trigger the one combination that produces the slowest, worst-case path. Static timing analysis avoids this problem entirely by checking delay algebraically instead of by simulating data.

A testbench triggering only a fraction of possible input states next to STA walking every path regardless of data value — Technical Reference DiagramWhy can't circuit simulation alone verify that a chip meets timing?

Technical Reference DiagramWhy can't circuit simulation alone verify that a chip meets timing?

Technical Explanation

Simulation is limited by whatever the testbench thinks to try.

State space is enormous. A 64-bit adder alone has 2^128 possible input combinations. No practical testbench simulates anywhere close to all of them, so a rare worst-case carry chain can simply never get triggered.
A path that's never exercised is a path that's never checked. If the testbench never asserts one rare condition, the slowest physical path through the logic stays hidden — and it can still exist in silicon even though simulation reported no problems.
Simulation doesn't scale to full chips. Gate-level simulation with real delays runs at only a handful of clock cycles per second. STA instead evaluates delay formulas directly, so its runtime scales with the number of gates and wires, not with how long the simulated program runs.
Multiplying by every corner makes it worse. A chip must work across dozens of process/voltage/temperature combinations. Re-running a slow simulation for each one is far too expensive to do exhaustively.

Common Mistake

The trap: assuming high functional coverage numbers (line, branch, or state-machine coverage) mean timing is also covered.
Coverage tools count which lines of RTL executed, not how slow the physical gates were when they did.
A path can execute thousands of times in simulation and still never be the one carrying the worst-case delay, so 100% functional coverage says nothing about timing closure.

Follow-up Question & Model Response

Given STA's blind spots, when is dynamic timing simulation actually still worth running?

Candidate Model Response: It earns its keep exactly where static analysis has no visibility — on asynchronous interfaces, clock-domain-crossing synchronizers, and power-up reset sequencing. Those behaviors depend on the order events happen in, not just how long a single path takes, and STA has no concept of event ordering across independent clocks. Simulation is also useful for double-checking specific paths the tool marked as exceptions, to make sure the false-path or multicycle assumption still makes functional sense.

Practical Example

On one automotive design, a FIFO's overflow flag never got asserted in three months of regression simulation, because the testbench never filled the buffer completely. Static timing analysis found the same path immediately once the circuit was built — the tool reported it as a −140 ps setup violation on the very first signoff run, since it doesn't need the FIFO to actually overflow to compute the delay along that path.

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