ExpertQuestion 38 of 69

How would you influence upstream teams (RTL, synthesis, library) to improve design-data quality for PrimeTime?

From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide

By Tabish Iqbal, who has 9+ years of VLSI Physical Design experience

Short Answer

Push the library team toward accurate, correctly-versioned characterization with the node's real models; the synthesis team toward a clean, linkable netlist and a shared constraint source; the RTL team toward clean, documented clocking; and establish shared naming and versioning conventions plus a fast feedback loop so a defect is reported and fixed at its source, not patched downstream on every run.

Upstream data-quality pipeline: RTL clocking documentation, synthesis netlist naming, and library characterization all feeding link_design, with defects reported back to source instead of patched downstream — Technical Reference DiagramHow would you influence upstream teams (RTL, synthesis, library) to improve design-data quality for PrimeTime?

Technical Reference DiagramHow would you influence upstream teams (RTL, synthesis, library) to improve design-data quality for PrimeTime?

Technical Explanation

PrimeTime's (PT) accuracy is entirely determined by the data handed to it, so influence has to reach the teams that produce that data before it reaches signoff.

With the library team. Ask for well-characterized, correctly-versioned libraries with accurate delay tables and the models the node needs — CCS timing and, where used, POCV data. Consistent cell and pin naming avoids link-time surprises. Clear version control and release notes ensure the intended libraries are the ones loaded. Validation that no cells or arcs are missing matters because a missing arc becomes an unresolved reference, or silently wrong timing with no error at all.
With the synthesis team. Ask for a clean, linkable netlist — no cell the loaded libraries do not provide, and cell naming consistent with the library so link_design (PT) resolves every instance. A shared constraint source matters too: signoff should verify against the same SDC synthesis optimized to.
With the RTL team. Ask for clean design structure and documented clocking and operating modes, so constraints are groundable in the design's real behavior, plus STA-friendly coding practices that avoid ambiguous or undocumented clock relationships.
Across all three, agree shared conventions. Naming, versioning, and handoff-format conventions mean data moves into PrimeTime without rework at each stage boundary.
Close the feedback loop. Reporting data-quality problems — unresolved references from link_design (PT), library gaps, netlist issues — back upstream promptly gets them fixed at the source, rather than patched in the signoff flow every run.
The argument that carries the most weight: the library is the model the analysis computes with, and the netlist is the design it assembles from that model — a defect in either produces wrong results, usually silently, with no error pointing back to the real cause.

Common Mistake

The Trap: patching a recurring upstream data-quality issue inside the signoff flow itself — a script that renames a handful of mismatched cell instances, or manually adds a missing timing arc override — instead of reporting it back to the owning team.

The local patch works for this run, but the same defect ships again next tapeout, next project, and next engineer who inherits the flow, because the source was never fixed.
A defect patched only downstream also never shows up in the upstream team's own quality metrics, so nothing motivates them to fix the root cause.

Follow-up Question & Model Response

"The synthesis team pushes back, saying their netlist already passes their own checks. How would you make the case that a data-quality issue still exists?"

Candidate Model Response: I would bring a specific, reproducible link_design (PT) failure or a specific cell instance PrimeTime cannot resolve against the released library, rather than a general complaint — a concrete unresolved reference is hard to argue with. I would also point out that synthesis's own checks and PrimeTime's linking are two different validations against two different criteria, so passing one does not guarantee passing the other, and the goal is aligning both against the same library and constraint source rather than treating either check as sufficient on its own.

Practical Example

A block-level netlist from synthesis instantiates a low-power isolation cell variant, ISO_CELLX2, that the signoff library release only provides as ISO_CELL_X2 — a single underscore-placement mismatch. link_design (PT) reports an unresolved reference for every instance of that cell, and the signoff engineer's first instinct is to add a local Tcl alias mapping one name to the other so the run completes. Reporting the mismatch to the synthesis team instead reveals their cell-naming script was pulling from an older library release; fixing the script at the source eliminates the mismatch for every future block that uses the same isolation cell, rather than requiring the same alias workaround on every signoff run going forward.

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