How do you build a power state table using create_pst and add_pst_state?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
First give each supply port its named states with add_port_state (UPF), then declare the table and its column order with create_pst (UPF), then add one row per legal mode with add_pst_state (UPF). Any combination you do not list is illegal. All three commands are legacy in IEEE 1801-2015, which recommends add_power_state (UPF) instead, but ICC2 and PrimeTime still read them.
Technical Explanation
- Port states:
add_port_state VDDdsp -state {DSP_HV 1.1} -state {DSP_LV 0.9}(UPF) names each voltage a supply can take, or off. - Table:
create_pst MYCHIP_pst -supplies {...}(UPF) fixes the column order once. - Rows:
add_pst_state PM3 -pst MYCHIP_pst -state {...}(UPF) lists one state per supply, in the same column order. - Why it matters: the table decides which crossings can see an off or lower-voltage driver, so it drives isolation and level-shifter checks.
- Isolation insertion follows the
set_isolationstrategies, not the table; ICC2 reports mismatches withcheck_mv_design(ICC2). - A missing legal row makes a real mode look illegal; an extra row demands cells you do not need.
# [UPF] mychip.upf
add_port_state VDD1p0 -state {HV 1.0}
add_port_state VDD0p9 -state {LV 0.9}
add_port_state VDDdsp -state {DSP_HV 1.1} -state {DSP_LV 0.9}
add_port_state PD_COP_SW/VDD -state {COP_ON 1.0} -state {COP_OFF off}
create_pst MYCHIP_pst -supplies {VDD1p0 VDD0p9 VDDdsp PD_COP_SW/VDD}
add_pst_state PM1 -pst MYCHIP_pst -state {HV LV DSP_HV COP_ON}
add_pst_state PM2 -pst MYCHIP_pst -state {HV LV DSP_LV COP_ON}
add_pst_state PM3 -pst MYCHIP_pst -state {HV LV DSP_HV COP_OFF}
add_pst_state PM4 -pst MYCHIP_pst -state {HV LV DSP_LV COP_OFF}
# [ICC2] icc2_shell
report_pstWhat To Check
- Every supply in -supplies has port states defined first.
- Each row lists exactly one state per column, in column order.
- Every mode the chip can enter, including wake-up transitions, has a row.
- No row keeps PD_COP on while an always-on supply it needs is off.
Command Checks & Actions
create_pst MYCHIP_pst -supplies {VDD1p0 VDD0p9 VDDdsp PD_COP_SW/VDD}Declare the table and its column order (legacy)
add_pst_state PM3 -pst MYCHIP_pst -state {HV LV DSP_HV COP_OFF}Add one legal mode (legacy)
report_pstPrint the table the tool actually read
report_pst -derivedShow the merged system-level states the tool derived
check_mv_designReport strategies that do not match the legal states
Healthy, Suspicious & Hard-stop Results
- Healthy (illustrative): report_pst shows four rows, PM1 to PM4, with COP_OFF only in PM3 and PM4.
- Suspicious (illustrative): report_pst -derived shows a combination you never listed; find its source before trusting isolation coverage.
- Hard stop: A row with the wrong number of entries fails to load, or a mode the firmware uses is missing.
Common Mistake
The Trap: Leaving out a mode the chip really enters, such as PD_DSP at DSP_LV while PD_COP wakes up.
- The tools treat that real state as illegal, so crossings that need protection in it are never checked.
What The Interviewer Is Testing
- Can you build a PST in the right order: port states, table, rows?
- Do you know the PST commands are legacy and what replaces them?
Follow-up Question & Model Response
"How would you write the same intent with add_power_state?"
Candidate Model Response: You give each supply set its states, for example SS_COP with COP_ON and COP_OFF through -supply_expr. You then create a power state group and add system states such as PM3 with a -logic_expr over the supply set states. The result is the same set of legal modes, but tied to supply sets instead of ports. That is the form IEEE 1801-2015 recommends, covered in the add_power_state question.
Practical Example
Design Scenario: (illustrative) MYCHIP has VDD1p0 at 1.0 V and VDD0p9 at 0.9 V always on, VDDdsp at 1.1 V or 0.9 V, and PD_COP_SW/VDD on or off. That gives four legal modes, PM1 to PM4. PM3 and PM4 put PD_COP off, so every PD_COP output needs isolation in those rows. PM2 and PM4 run the DSP at 0.9 V, so DSP crossings into the 1.0 V top need up-shifting there.
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