Level 2: Construction & Debugging

Intermediate Low Power Interview Questions

Construct and validate UPF strategies, cell mapping, hierarchy, power states, always-on paths, and implementation reports.

0 of 60 marked complete

Want all 1109 answers offline as 4 PDF books?

See the 4-book bundle · ₹349 Low-Power & UPF Handbook Complete library

What to practise at this level

Construct and validate UPF strategies, cell mapping, hierarchy, power states, always-on paths, and implementation reports.

01 How do you create a power domain in UPF, and what does the create_power_domain command actually do?Intermediate: `create_power_domain` (UPF) names a group of instances that share one primary supply and one set of isolation, level-shifter and retention strategies. It is bookkeeping for the tools, not a netlist cell: nothing gets inserted until strategies act on it. In MYCHIP you create the always-on top domain, then one child domain per block, and confirm the result with `report_power_domains` (ICC2).
02 How do you create supply ports and supply nets for a power domain?Intermediate: You create the entry points with `create_supply_port` (UPF), the wires with `create_supply_net` (UPF), and join them with `connect_supply_net` (UPF). A net created for one domain can be extended into another with `-reuse`, so one physical rail spans the hierarchy. In IEEE 1801-2015 you then bundle nets into supply sets instead of naming them as domain primaries directly.
03 What is a supply set in UPF, and how is it different from a plain supply net?Intermediate: A supply net is one wire carrying one function, such as VDD1p0 or GND. A supply set is a named bundle of functions (power, ground, and optionally nwell and pwell) that you bind to real nets, so a strategy can say "power this from SS_AON" without listing nets. IEEE 1801-2015 builds domain primaries, isolation supplies and retention supplies on supply sets, created with `create_supply_set` (UPF).
04 How do you connect a supply net to a domain's primary power/ground using set_domain_supply_net?Intermediate: `set_domain_supply_net` (UPF) names the primary power and ground nets of a domain, and every cell in that domain is then implicitly tied to them. IEEE 1801-2015 lists it as legacy: the modern form binds a supply set with `create_power_domain PD_COP -supply {primary SS_COP}` (UPF). Both still load in ICC2 and PrimeTime, so you need to read the old form and write the new one.
05 How do you write an isolation strategy with set_isolation, and what do its key options control?Intermediate: `set_isolation` (UPF) tells the tool which boundary ports of a switchable domain need an isolation cell, what powers that cell, and what value it holds while the domain is off. Pair it with a control signal, and the always-on side never sees a floating input.
06 What isolation placement locations are available (self, parent, fanout, automatic), and how do you choose between them?Intermediate: For `set_isolation` (UPF), IEEE 1801-2015 lists four locations: self (the default), parent, other and fanout; automatic is a `set_level_shifter` (UPF) value in ICC2, not an isolation one. The location decides which domain hosts the cell, and therefore which rail its row gives it. Choose the site where the isolation supply is already on, so you avoid a dual-rail cell and a secondary strap inside a switched area.
07 What are the different isolation clamp values (0, 1, latch), and when would you use each?Intermediate: The clamp value is what the isolation cell drives while its source domain is off: 0 (an AND-type cell, the ICC2 default), 1 (an OR-type cell) or latch (holds the last value). Choose it signal by signal, from what the always-on receiver treats as inactive, not one value per domain. Active-high enables clamp to 0, active-low resets clamp to 1, and buses that must keep their last value use latch.
08 How do you write a level-shifter strategy with set_level_shifter, and what do its key options control?Intermediate: `set_level_shifter` (UPF) tells the tool which ports of a domain get level shifters, for which voltage direction, and in which domain the cell sits. Low-to-high crossings always need a shifter; high-to-low ones depend on the library and the voltage gap, which is what `-rule` and `-threshold` let you filter. Without any strategy, ICC2 still inserts shifters from the voltages in the power states.
09 How do you decide between placing a level shifter in "self" vs "parent" location?Intermediate: Pick the side where the shifter can get both supplies cheaply: its row rail gives one supply and a secondary pin must reach the other. Self puts the cell inside the domain whose port is shifted; parent puts it in the surrounding domain. For MYCHIP, up-shifters on PD_CPU outputs usually sit in the parent, and down-shifters on PD_CPU inputs sit in self.
10 How do you write a retention strategy with set_retention, and what supplies does it need?Intermediate: `set_retention` (UPF) names which registers in a shutdown domain must keep their state, which supply keeps that state alive, and which signals save and restore it. The register needs two supplies: the switched primary for normal operation and a retention supply that stays on while the primary is off. In IEEE 1801-2015 you give that supply as a set with `-retention_supply` and put the save and restore signals on the same command.
11 How do you specify save and restore signals with set_retention_control?Intermediate: You name each control net and its active level or edge: `-save_signal {U_PC/SAVE high}` and `-restore_signal {U_PC/NRESTORE low}`. In IEEE 1801-2015 these options sit on `set_retention` (UPF) itself; `set_retention_control` (UPF) is the UPF 1.0 form that ICC2 and PrimeTime still accept. The sense you write must match the retention cell pins, or the flop saves and restores at the wrong moments.
12 How do you create a power switch with create_power_switch, and what are its input/output/ control ports?Intermediate: `create_power_switch` (UPF) declares an abstract switch that passes an always-on input supply to a switched output supply under a control signal. You name its ports and the nets they connect to, then write Boolean on and off states in terms of the control port. It is one abstract switch in the UPF, later mapped to library cells and built as an array of many cells.
13 How do you map an abstract UPF power switch to a real library cell with map_power_switch?Intermediate: `map_power_switch` (UPF) tells the tools which library cell implements an abstract switch from `create_power_switch` (UPF). In IEEE 1801-2015 the syntax is the switch name followed by a required `-lib_cells` list and an optional `-port_map`. Mapping picks the cell; ICC2 still has to build and connect the physical array.
14 How does a "virtual rail" get created in practice -walk through the switched supply net in the Mychip example.Intermediate: No single UPF command creates a virtual rail. You declare a separate supply net, make it the output of a power switch fed by the always-on rail, and bind it as the primary of the shutdown domain. In MYCHIP that net is VDD1p0_SW: the switch PD_COP_SW drives it from VDD1p0, and PD_COP runs on it through the supply set SS_COP.
15 How do you build a power state table using create_pst and add_pst_state?Intermediate: First give each supply port its named states with `add_port_state` (UPF), then declare the table and its column order with `create_pst` (UPF), then add one row per legal mode with `add_pst_state` (UPF). Any combination you do not list is illegal. All three commands are legacy in IEEE 1801-2015, which recommends `add_power_state` (UPF) instead, but ICC2 and PrimeTime still read them.
16 What are always-on control paths and always-on buffers used for in a real design?Intermediate: Always-on control paths carry the signals that manage a shutdown domain, such as isolation enable, save, restore and switch enable, and they must keep working while that domain is off. When such a path runs through a switched voltage area and needs buffering, it needs always-on buffers: cells with a backup supply pin that stays on. ICC2 inserts and legalizes them itself, but only if the library has always-on buffers and the backup supply can reach them.
17 What is a feedthrough path, and what happens if it isn't handled correctly?Intermediate: A feedthrough path is a net that passes through a domain without being used there, for example a PD_CPU to PD_MYCHIP signal routed across the PD_COP area. If it gets buffered on the switched supply of the area it crosses, the net dies whenever that domain is off, even though both its ends are on. ICC2 handles this with always-on or dual-rail buffers, and the UPF can also mark ports that are shorted inside a block as feedthroughs.
18 How is UPF hierarchy built for nested/composite power domains?Intermediate: Hierarchy in UPF comes from scope: every command acts in the current scope, and you move it with `set_scope` (UPF) or run a block file in place with `load_upf -scope` (UPF). A domain created in a lower scope whose elements sit inside a parent domain simply nests there. `create_composite_domain` (UPF) groups several domains under one name for shared strategies, but it has no physical region.
19 What library cell attributes does a low-power cell need to have (e.g. is_isolation_cell, is_level_shifter, switch_cell_type)?Intermediate: The tool only uses a cell for isolation, level shifting, switching, retention or always-on buffering if its Liberty model says so. Each type has a cell flag, such as is_isolation_cell or is_level_shifter, plus pin attributes that mark enable pins, PG pin types and which supply each signal pin belongs to. You check what the tool actually read with `report_mv_lib_cells` (ICC2).
20 What commands would you use to generate a basic low-power implementation report (e.g. report_power_domains, report_mv_cells, report_pst)?Intermediate: Start with what the tool resolved: `report_power_domains` (ICC2), `report_supply_sets` (ICC2) and `report_pst` (ICC2). Then check what it built with `report_mv_cells` (ICC2) and judge the result with `check_mv_design` (ICC2). Repeat the domain and supply reports in PrimeTime so signoff reads the same intent.
21 What are ECRL and PFAL, and how do they implement adiabatic charging in a real gate?Intermediate: ECRL (Efficient Charge Recovery Logic) and PFAL (Positive Feedback Adiabatic Logic) are dual-rail adiabatic gate families. Instead of a fixed VDD, each gate hangs off a slowly ramping power-clock, so the output charges gently and most of the charge flows back to the supply when the clock ramps down. They differ in where the logic trees sit and how cleanly the outputs swing, and both need a multi-phase power-clock generator that standard ASIC flows do not provide.
22 What is AVS (Adaptive Voltage Scaling), and how does closed-loop feedback make it different from open-loop DVFS?Intermediate: AVS trims a domain's supply voltage in a closed loop, using on-die monitors that measure how fast this particular die is right now. DVFS picks a voltage from a fixed table built for the slowest die at the worst temperature, so it wastes margin on typical and fast silicon. AVS runs on top of DVFS: DVFS chooses the frequency, and AVS finds the lowest voltage that still meets it.
23 What is VTCMOS (Variable Threshold CMOS), and how does dynamically biasing the body reduce leakage?Intermediate: VTCMOS changes transistor threshold voltage at runtime by driving the wells from a body-bias generator instead of tying them to VDD and VSS. In standby it applies reverse body bias to raise Vt and cut subthreshold leakage, and in active mode it returns to zero or forward bias for full speed. The block keeps its state because the supply stays on; only the wells move.
24 What is DTCMOS (Dynamic Threshold CMOS), and how does tying the body to the gate differ from VTCMOS?Intermediate: DTCMOS ties each transistor's body to its own gate, so the threshold voltage follows the input. When the gate turns the device on, the body forward-biases and Vt drops for more drive; when the gate is off, the body returns to the source level and Vt stays high for low leakage. There is no bias generator, but the supply must stay below the body diode turn-on voltage, which limits DTCMOS to very low-voltage designs.
25 What is the difference between light-sleep, deep-sleep, and full shutdown retention states for on-chip memory, and what do they trade off?Intermediate: Light sleep, deep sleep and shutdown are three increasingly deep memory power modes. Each one saves more leakage than the one before and takes longer to wake, and only shutdown loses the stored data. The right choice depends on how long the memory will stay idle compared with the energy and time it costs to wake it up.
26 What is the difference between fine-grain and coarse-grain clock gating, and what does an integrated clock gating (ICG) cell do that a plain AND gate cannot?Intermediate: Fine-grain clock gating stops the clock to a small group of registers that share an enable, usually inserted by synthesis from RTL enable logic. Coarse-grain gating stops the clock at a branch or block root, so the buffers under it stop toggling too. Both use an ICG cell, which latches the enable while the clock is low so the gated clock never glitches, something a bare AND gate cannot guarantee.
27 What is the difference between UPF (IEEE 1801) and CPF (Si2) as power-intent languages, and why did the industry converge on UPF?Intermediate: UPF and CPF are both Tcl-based languages that describe power intent outside the RTL: domains, supplies, isolation, level shifting, retention and power states. UPF started at Accellera and became IEEE 1801, while CPF came from the Si2 consortium with Cadence behind it. The industry settled on UPF because an IEEE standard gave every tool vendor a single target, and Cadence tools now read UPF too, so a UPF file travels across vendors.
28 How do you create a voltage area, and why add a guard band?Intermediate: `create_voltage_area` (ICC2) turns a UPF power domain into a physical region where that domain's cells must be placed; the placer treats it like an exclusive move bound. A guard band is a hard keepout ring that grows outward from the voltage area edge, where no cell can sit. It keeps cells of neighbouring domains apart so their power rails and straps can be built without shorts.
29 How do nested or rectilinear voltage areas work, and which shape wins where they overlap?Intermediate: Where voltage-area shapes overlap, ICC2 uses stacking order: by default the shape defined last sits on top and owns the overlap. To nest one voltage area inside another, you define the outer one first and the inner one second, so the inner shape is on top and the outer area's effective shape becomes a ring. Define them the other way round and the outer shape masks the inner one, which ends up with no placement area at all.
30 When can two power domains share one voltage area?Intermediate: Two power domains can share one voltage area when their primary supplies are equivalent: connected in the UPF, physically connected, or functionally equivalent with the same power states. You declare the sharing with the `shared_voltage_area` design attribute through `set_design_attributes` (UPF), and one of the domains acts as the primary domain. The shared voltage area gets one power switch implementation, and `connect_power_switch` (ICC2) wires it for all domains in the set.
31 Should you implement power switches as an array or a ring?Intermediate: An array spreads switch cells in columns or a grid through the voltage area, so every standard cell is close to a switch and IR drop stays low. A ring places the switches along the voltage-area boundary, which keeps the core rows free but makes the centre the farthest point from any switch. Arrays suit large or high-current domains; rings suit small domains and hard macros that cannot take switch cells inside.
32 How are power-switch cells daisy-chained, and why?Intermediate: In a daisy chain, the switch enable enters the first switch cell, and each cell passes a buffered copy to the next, so the switches turn on one after another instead of all at once. That spreads the in-rush current that charges the virtual rail over time and keeps the peak within what the grid can deliver. The output of the last cell comes back as the acknowledge, telling the power controller that every switch is on.
33 What are secondary PG placement constraints, and why does ICC2 need them?Intermediate: Dual-rail cells in a shutdown domain, such as always-on buffers, isolation cells and level shifters, need a nearby strap for their secondary (backup) supply. By default ICC2 assumes that strap exists everywhere in the voltage area, which is rarely true. Secondary PG placement constraints tell the placer where the straps really are, so dual-rail cells land close enough for short, low-IR secondary PG routes.
34 How do you buffer an always-on net that runs through a shutdown domain?Intermediate: Buffers placed inside a shutdown voltage area on an always-on net must stay powered when the domain is off. You use dual-rail always-on buffers whose backup power pin connects to an always-on secondary supply, never single-rail buffers on the switched rail. ICC2 does this automatically during optimization, and `fix_mv_design -buffer` (ICC2) and `create_mv_cells -always_on` (ICC2) repair buffers that are on the wrong supply.
35 What's the difference between physical and logical feedthrough buffering in multivoltage designs?Intermediate: Both methods buffer a net that physically crosses another domain's voltage area. Physical feedthrough buffering places dual-rail buffers in the crossed voltage area and assigns them to that power domain without punching ports, so the logic hierarchy is unchanged. Logical feedthrough buffering is used when the domain is created at a scope below the net, so the tool punches ports into that hierarchy and places the buffer inside it.
36 How does placement respect voltage areas, and what goes wrong at the boundaries?Intermediate: The placer treats each voltage area as an exclusive move bound: a domain's cells must go inside its voltage area, and every other cell must stay out. Isolation and level shifter cells follow their strategy location, so they collect along voltage-area edges, and dual-rail cells also need to sit near their secondary straps. Most boundary problems come from crowding at those edges, guard bands that eat space, and cells that end up in the wrong area after an ECO.
37 How do you build a clock tree that crosses power domains?Intermediate: A clock that enters a domain at a different voltage needs a level shifter like any other signal, but ICC2 does not insert level shifters on clock nets by default. You name the clock nets in `mv.upf.auto_ls_clock_nets` (ICC2) and allow shifting on ideal nets with `mv.upf.allow_ls_on_ideal_networks` (ICC2). Then you keep the shifted branch balanced, watch duty cycle, and make sure clock buffers feeding always-on logic stay on when their domain powers down.
38 How are the PG pins of dual-rail cells connected, and how do you check them?Intermediate: A dual-rail cell has its primary PG pins on the supply of the domain it sits in and its backup pin on the supply the UPF strategy names, such as the isolation supply. `connect_pg_net -automatic` (ICC2) derives those connections from the committed UPF and the library PG pin data, so you do not wire them by hand. You then check them with `check_mv_design -pg_netlist` (ICC2), because the default `check_mv_design` (ICC2) run skips PG net and PG connection checks.
39 What does `create_mv_cells` insert, and where does it sit in the flow?Intermediate: `create_mv_cells` (ICC2) inserts power management cells from the UPF strategies: isolation cells, level shifters and repeaters, and with its own options retention cells and always-on legalization of buffers. It runs after `load_upf` (ICC2) and before placement, and it is optional because synthesis normally inserts these cells, but it gives early feedback on whether the power intent is feasible. The flow then continues with `check_mv_design` (ICC2), placement and optimization, and `save_upf` (ICC2).
40 How do you read a `check_mv_design` report and triage what it finds?Intermediate: `check_mv_design` (ICC2) prints one section per rule group, from power domain and supply rules through strategy rules to cell rules, with each message followed by an MV-080 total for that message ID. Triage from the top: supply and domain problems cascade into everything below, so fix those first, then strategy conflicts, then individual cells. For any cell or path it flags, `report_mv_path` (ICC2) tells you why a cell was inserted, associated or rejected.
41 What does report_mv_path show, and when do you use it?Intermediate: `report_mv_path` (ICC2) traces one multivoltage path through a pin, net or cell and shows every MV cell on it with its supply, drivers, sinks, strategy and power domain. For a level shifter or isolation cell that failed to insert or associate, it prints the reason. You reach for it when `check_mv_design` (ICC2) flags a cell or net and you need to know why.
42 How do you confirm every crossing that needs isolation actually has it?Intermediate: Check functional and DFT crossings separately. For functional paths, run `check_mv_design -isolation` (ICC2), which checks isolation strategies, isolation cells and the isolation of the netlist, then trace anything it flags with `report_mv_path` (ICC2) to see which strategy applies and why a cell is missing or unassociated. Scan stitching adds crossings the RTL UPF never listed, so after scan insertion run `check_isolation_coverage -dft_signals` (ICC2), which reports DFT paths with an isolation violation that no strategy covers.
43 How do you keep implementing when the UPF isn't finished yet?Intermediate: Use the early data check manager: `set_early_data_check_policy` (ICC2) sets how each multivoltage check reacts (error, tolerate or repair), and `report_early_data_checks` (ICC2) lists what was relaxed and how often it fired. The older route is the incomplete UPF flow, enabled with `mv.incomplete_upf.enable` (ICC2). Either way the tool is guessing at missing intent, so every relaxed check must be closed before signoff.
44 How does PrimeTime use the UPF for timing?Intermediate: PrimeTime reads the UPF with `load_upf` (PT), builds a virtual model of the power network and pushes each supply net voltage down to the PG pins of every leaf cell. You give the voltages with `set_voltage` (PT), and each cell is then timed at its own supply voltage. PT does not read the power state table directly, so your voltages must match the one PST state you mean to verify.
45 How do level shifters affect timing, and what does PT check at a voltage crossing?Intermediate: A level shifter is a real cell on the path, and its delay depends on both its input and output supply voltages. PT times it from two-rail libraries characterized at voltage pairs, and separately checks signal levels with `check_timing -include signal_level` (PT) to catch crossings that need a shifter but lack one. `set_level_shifter_threshold` (PT) sets how large a driver-load voltage difference counts as a mismatch.
46 Why does the isolation enable have timing requirements, even though it's "just a control signal"?Intermediate: The isolation enable decides the moment the always-on side stops trusting a domain, so it is a timed event, not a static setting. It must reach every isolation cell and settle before the switched rail starts to fall, and it may only release once the rail is back, the domain is restored and its outputs are valid. The whole path that carries it must stay powered while the domain is off.
47 What does a low-power static checker like VC LP verify, and at which stages?Intermediate: A low-power static checker such as VC LP reads the design and the UPF and proves, without simulation, that the power intent is consistent and that the netlist implements it. You run `check_lp` (VCLP) by stage: `-stage upf` for the power intent, `-stage design` for the netlist, and `-stage pg` once the netlist carries power and ground pins. You then read `report_violations -app LP` (VCLP) and waive only what you can justify.
48 What is power-aware simulation, and what does "corruption" mean?Intermediate: Power-aware simulation runs your RTL or netlist together with the UPF, so supplies can switch off during a test. When a supply set enters a state whose simstate is CORRUPT, the simulator corrupts what it powers: state elements and the nets they drive go to X, and those processes stop evaluating. That turns a missing clamp, a controller that switches in the wrong order, or a retention register restored too early into visible X on signals your testbench already checks.
49 What changes for scan and DFT when the design has power domains?Intermediate: Scan stitching adds paths the functional UPF never saw: a chain that runs from PD_COP into PD_MYCHIP crosses a domain boundary and needs isolation and level shifting like any data signal. ICC2 covers these with `set_dft_isolation` (ICC2), which reuses an existing isolation strategy for DFT connections, or with a placeholder strategy that `generate_mv_constraints -dft_isolation` (ICC2) fills after `insert_dft` (ICC2). `check_isolation_coverage -dft_signals` (ICC2) then shows what is still uncovered.
50 What's the basic flow to get a signoff power number in PrimeTime?Intermediate: Enable PrimePower with `set_app_var power_enable_analysis true` (PT), load the routed netlist with parasitics, constraints and the UPF, read switching activity with `read_saif` (PT) or `read_vcd` (PT), then run `update_power` (PT) and `report_power` (PT). The number is only as good as the activity behind it, so use a simulation of a real use case, not assumed toggle rates. Report by group to see where the power goes.
51 What is glitch power, and how do you reduce it?Intermediate: Glitch power is the energy burned by spurious transitions: when the inputs of a gate arrive at different times, its output can toggle several times before it settles. Each extra toggle charges and discharges real capacitance, so it costs as much as a useful one, and in deep arithmetic logic those wasted edges add up to a real share of the block power. You reduce it by balancing path delays, cutting logic depth with pipelining, and stopping datapaths from toggling when their result is not needed.
52 Why do you care about peak power, not just average power?Intermediate: Average power sets battery life and steady temperature, but peak power sets what the package, the power grid and the regulator must survive in a single instant. A chip can meet its average budget and still fail when many blocks switch together or a domain wakes up and draws rush current. You plan and check both, because they break different things: average power drains the battery and heats the package, while a peak collapses the supply for a few nanoseconds and fails timing inside that window.
53 What are supply set handles, and how does associate_supply_set use them?Intermediate: A supply set handle is a named slot on a UPF object, such as a power domain or a strategy, that stands for the supply set used there. ICC2 gives every domain primary, default_isolation and default_retention handles, and `associate_supply_set` (UPF) binds a real supply set such as SS_AON to a handle so both resolve to the same nets. Writing strategies against handles keeps the intent readable and lets you rebind a supply without rewriting every strategy.
54 What changed between legacy UPF and IEEE 1801-2015, and why does add_power_state replace the PST?Intermediate: IEEE 1801-2015 Annex D marks the PST commands `create_pst` (UPF), `add_pst_state` (UPF) and `add_port_state` (UPF), plus `set_domain_supply_net` (UPF) and the net-based isolation and retention supply options, as legacy, and names a replacement for each. The PST gives way to `add_power_state` (UPF), which defines states on supply sets and domains instead of in one flat table. Tools still accept both forms, and interviews ask about both.
55 How do you tell the tools which supply drives or receives a top-level port?Intermediate: Use `set_port_attributes` (UPF) with `-driver_supply` on inputs and `-receiver_supply` on outputs to say which supply set drives or reads a top-level port; `set_related_supply_net` (UPF) does the same job with supply nets. The tools compare that supply with the domain on the inside to decide whether isolation or a level shifter is needed. Get it wrong and you get missing cells on real crossings, or extra cells on crossings that do not exist.
56 How do you force a specific library cell for an isolation or level-shifter strategy?Intermediate: Use `use_interface_cell` (UPF) to tie an isolation strategy, a level-shifter strategy, or one of each to the library cells you list. It is the only mapping command that can map a combined cell such as an enable level shifter, and in ICC2 it wins over `map_isolation_cell` (UPF) and `map_level_shifter_cell` (UPF) on the same strategy. Then check with `report_mv_lib_cells` (ICC2) that the forced cell really has the attributes the strategy needs.
57 What's the difference between single-rail and dual-rail isolation cells, and when is each used?Intermediate: A single-rail isolation cell has one power pin and runs from the rail of the domain it sits in, so it must sit where that rail stays on during shutdown. A dual-rail cell adds a backup power pin fed by an always-on supply, which lets it sit inside the domain that switches off and keep clamping. ICC2 picks between them from the cell rail information and the location of the strategy, and warns when the choice looks wrong.
58 What are two-pin, single-pin and zero-pin retention registers?Intermediate: They differ in how many retention control pins they have. A two-pin register has separate SAVE and RESTORE pins, a single-pin register uses one save_restore pin whose level selects the mode, and a zero-pin register has no control pin because its subordinate latch sits on an always-on supply. Zero-pin registers only retain if the clock and asynchronous pins are held inactive, so ICC2 inserts clamp cells that you must check.
59 How do you size power-switch cells against an IR-drop target?Intermediate: Run a voltage-drop analysis with RedHawk Fusion, give each switch cell its on-resistance with `set_power_switch_resistance` (ICC2), then run `size_power_switches -max_irdrop` (ICC2) with your drop target. The tool swaps switches for same-footprint cells of a different Vt to meet the target, and skips any switch it cannot improve. You trade drop against switch leakage and area, so check both after the swap.
60 How does multi-Vt leakage recovery work in a real flow?Intermediate: You close timing with a low-Vt-heavy mix, then swap cells on paths with spare slack to higher-Vt versions of the same footprint, which leak far less. The implementation tool does this during optimization, and PT does it again at signoff with `fix_eco_power` (PT), which backs out any change that creates a timing or DRC violation. You keep a slack guard band, so later crosstalk and variation do not eat the paths you just slowed.

Preparing for a physical design interview? Take the answers with you.

All 1109 questions and answers as 4 PDF books: PnR, STA, MMMC and Low Power.
A clickable table of contents, so you can search and jump offline.
Delivered by email within seconds of payment. Full refund if the files fail to arrive or open.

See what is inside the bundle · ₹349 Low-Power & UPF Handbook Complete library