What is a power state table?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
A power state table (PST) lists the combinations of supply values the chip is allowed to be in at the same time. Each row is one legal mode, such as all domains on, or the GPU off while the CPU runs at low voltage. Implementation and checking tools use it to decide which crossings need level shifters and isolation.
Technical Explanation
- Each supply gets a small set of named states, such as 0.8 V, 1.0 V or OFF.
- A power state row combines one state per supply into a mode the chip really uses.
- Tools read the table to find crossings where the driver can be off while the receiver is on, which is where isolation goes.
- They also find pairs of supplies at different voltages, which is where level shifters go.
- Combinations you leave out are treated as unreachable, so a missing row hides real violations.
- The table lives once in the UPF and is read by synthesis, ICC2, PrimeTime and the static checker, so every tool sees the same modes.
- In IEEE 1801-2015,
add_power_state(UPF) is the current way to write states. Legacy form (still accepted by ICC2/PT):create_pst(UPF) plusadd_pst_state(UPF).
Common Mistake
The Trap: Writing only the modes you think about day to day and forgetting a real one, such as GPU off during CPU turbo.
- The tools never see that combination, so a crossing that needs isolation in that mode is left unprotected.
- Nothing flags it in implementation; it surfaces as an X in power-aware simulation, or as a failure in silicon in that one mode.
Follow-up Question & Model Response
"What happens if the table lists a combination that can never occur?"
Candidate Model Response: Nothing breaks functionally, but the tools must protect against it anyway. You can end up with extra isolation or level shifter cells that cost area and delay. The fix is to remove the row or mark the state illegal. Keep the table close to the real modes the power controller can reach. report_system_pst (VCLP) prints the table the static checker built, which is a quick way to compare it with the spec.
Practical Example
Design Scenario: (illustrative) Three supplies: VDD_AON at 0.9 V, VDD_CPU at 0.8 V or 1.0 V, and VDD_GPU_SW that is ON or OFF. The legal rows are TURBO (0.9, 1.0, ON), NOMINAL (0.9, 0.8, ON) and GPU_OFF (0.9, 0.8, OFF). A row with VDD_AON OFF and the others on is illegal, since the power controller lives on VDD_AON. Because GPU_OFF exists, every GPU output that feeds CPU or AON logic needs isolation.
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