ExpertQuestion 1 of 50

Walk through the complete "Mychip" multivoltage architecture: what are its power domains, and how do they relate to each other?

From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide

By Tabish Iqbal, who has 9+ years of VLSI Physical Design experience

Short Answer

MYCHIP has four power domains: the always-on top PD_MYCHIP on VDD1p0 (1.0 V), an always-on PD_CPU on VDD0p9 (0.9 V), a switchable PD_COP on VDD1p0_SW with retention, and PD_DSP on an external rail VDDdsp that moves between 1.1 V and 0.9 V. The power controller U_PC sits in PD_MYCHIP, drives PSE, ISE and SRE, and reads PSE_ACK back from the PD_COP switch. Every crossing then needs its own strategy: a level shifter where voltages differ, isolation where the driver can be off while the receiver is on.

Floorplan of MYCHIP: tinted always-on PD_MYCHIP (VDD1p0, 1.0 V) holding PD_CPU (VDD0p9, 0.9 V), hatched switchable PD_COP (VDD1p0_SW) and tinted PD_DSP on the external rail VDDdsp (1.1 or 0.9 V); U_PC drives PSE, ISE and SRE and reads PSE_ACK, and each crossing is marked LS, ISO or LS+ISO. — Technical Reference DiagramWalk through the complete "Mychip" multivoltage architecture: what are its power domains, and how do they relate to each other?

Technical Reference DiagramWalk through the complete "Mychip" multivoltage architecture: what are its power domains, and how do they relate to each other?

Technical Explanation

PD_MYCHIP is the always-on root on VDD1p0 at 1.0 V. It owns the chip glue and the power controller U_PC.
PD_CPU (U_CPU) stays on at 0.9 V from VDD0p9, so every CPU output into the top crosses 0.9 V to 1.0 V.
PD_COP (U_COP) runs on VDD1p0_SW, the output of a header switch on VDD1p0, and keeps state in retention flops powered from VDD1p0.
PD_DSP (U_DSP) takes the external rail VDDdsp at 1.1 V or 0.9 V, so its crossings into 1.0 V logic change direction with the DSP mode.
U_PC drives PSE (switch enable), ISE (isolation enable) and SRE (save/restore) and waits for PSE_ACK. All four nets must stay in always-on logic.
A wrong crossing fails quietly: a missing isolation cell floats a 1.0 V input while PD_COP is off, and a missing shifter leaves a 0.9 V high marginal.
Legacy form (still accepted by ICC2/PT): create_power_domain PD_MYCHIP -include_scope (UPF) and set_domain_supply_net (UPF) for each primary supply.

# [UPF]  mychip.upf
create_power_domain PD_MYCHIP -elements {.}
create_power_domain PD_CPU -elements {U_CPU}
create_power_domain PD_DSP -elements {U_DSP}
create_power_domain PD_COP -elements {U_COP} -supply {primary SS_COP}
set_isolation ISO_COP -domain PD_COP -applies_to outputs -isolation_supply SS_AON -clamp_value 0 -isolation_signal ISE -isolation_sense high
set_level_shifter LS_CPU -domain PD_CPU -applies_to outputs -rule low_to_high
# [ICC2]  icc2_shell
load_upf mychip.upf
commit_upf
check_mv_design

What To Check

Every instance, U_PC included, sits in exactly one domain before commit_upf (ICC2).
Each crossing has what it needs: LS from PD_CPU to the top, ISO out of PD_COP, both where PD_COP drives PD_DSP, whose voltage differs from 1.0 V in both modes.
Isolation and retention supplies point at VDD1p0 (SS_AON), never at VDD1p0_SW.
PSE, ISE, SRE and PSE_ACK are driven and buffered by always-on logic.

Command Checks & Actions

UPF (design.upf)create_power_domain PD_COP -elements {U_COP} -supply {primary SS_COP}

Puts U_COP in the switchable domain with its switched supply set as primary

UPF (design.upf)

set_isolation ISO_COP -domain PD_COP -applies_to outputs -isolation_supply SS_AON -clamp_value 0 -isolation_signal ISE -isolation_sense high

Clamps PD_COP outputs to 0 from the always-on supply while ISE is high

ICC2 (icc2_shell)load_upf mychip.upf

Reads the power intent into the design

ICC2 (icc2_shell)report_power_domains

Lists each domain with its extent and primary supply

ICC2 (icc2_shell)check_mv_design

Reports missing isolation, missing level shifters and wrong supply connections

Healthy, Suspicious & Hard-stop Results

Healthy (illustrative): report_power_domains (ICC2) shows four domains with U_PC in PD_MYCHIP, and check_mv_design (ICC2) reports no isolation or voltage violations.
Suspicious (illustrative): check_mv_design (ICC2) flags a PD_CPU output crossing 0.9 V to 1.0 V with no level shifter.
Hard stop: U_PC ends up outside PD_MYCHIP, or ISO_COP uses VDD1p0_SW as its supply: the controller or the clamps die with PD_COP.

Common Mistake

The Trap: Treating PD_DSP as a fixed-voltage domain and writing only a high-to-low shifter rule for its outputs.

In the 0.9 V DSP mode the same net becomes a low-to-high crossing, and the 1.0 V receiver sees a weak high.
The bug shows up in one DSP mode only, so a check run in a single mode passes it.

What The Interviewer Is Testing

Whether you can turn an architecture drawing into a crossing-by-crossing strategy list.
Whether you know the controller and every isolation and retention supply must be always-on.

Follow-up Question & Model Response

"Why must U_PC sit in PD_MYCHIP rather than inside PD_COP?"

Candidate Model Response: U_PC is the logic that turns PD_COP back on. If it lived in PD_COP it would lose power the moment PSE dropped, and nothing would be left to raise PSE again. Its ISE and SRE outputs also have to hold steady during shutdown, which only an always-on supply can guarantee. In the always-on root it survives every power mode.

Practical Example

Design Scenario: (illustrative) In a sleep mode PD_COP is off, PD_CPU runs at 0.9 V and VDDdsp sits at 0.9 V. The PD_COP output cop_done feeds PD_MYCHIP logic, so ISO_COP clamps it to 0 while ISE is high. The DSP interrupt dsp_irq crosses 0.9 V to 1.0 V and needs a low-to-high shifter; in the 1.1 V DSP mode the same net crosses high to low. Cell names such as ISO_AND_X1 and LS_LH_X1 are illustrative.

Low-Power & UPF Handbook