Can you give an example of a chip with multiple power domains?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
A phone SoC is the classic example: the big CPU cluster, the GPU and the modem each sit in their own switchable domain, and a small always-on domain keeps the power controller, real-time clock and wake-up logic alive. Each switchable domain turns off or scales its voltage based on what the phone is doing. The always-on domain decides when they come back.
Technical Explanation
- CPU cluster domain: scales voltage and frequency with load and powers off entirely when the phone sleeps.
- GPU domain: off except when drawing; runs at its own voltage to meet frame rate.
- Modem domain: wakes on a timer to check for network pages, then shuts down again.
- Always-on domain (AON): power controller, interrupt and wake logic, RTC; tiny, HVT-heavy and never switched.
- Every signal from a switchable domain into AON needs isolation, and every crossing between voltages needs a level shifter.
- Domains follow use cases: blocks that sleep and wake together share a domain, which keeps the domain count and boundary cells down.
- If the power controller lived in a switchable domain, nothing could turn that domain back on.
Common Mistake
The Trap: Putting the wake-up or interrupt logic in a domain that can be switched off.
- The chip goes to sleep and never wakes, a bug that simulation without power-aware modelling will not catch.
- Put every wake source, such as the timer, interrupts and the power button, in the always-on domain, and prove wake-up in power-aware simulation.
Follow-up Question & Model Response
"How would the same idea apply to MYCHIP?"
Candidate Model Response: PD_MYCHIP plays the always-on role and holds the power controller U_PC. PD_CPU stays on at 0.9 V, PD_COP is power-gated with retention, and PD_DSP has an externally switched supply. U_PC drives the switch enable and reads its acknowledge, and drives the isolation enable and the save/restore enable for PD_COP. The structure is the phone SoC in miniature.
Practical Example
Design Scenario: (illustrative) In standby, only PD_AON at 0.8 V is on, drawing 2 mW. On a network page, PD_MODEM powers up for 20 ms, then goes off. When the user opens a game, PD_CPU_BIG ramps to 1.0 V and PD_GPU turns on at 0.75 V. Signals from PD_GPU into PD_AON need isolation, and the 0.75 V to 0.8 V low-to-high crossings need level shifters. Check the standby budget: 2 mW for 20 hours is 40 mWh, while a modem left on at 30 mW would burn 600 mWh in the same time.
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