What is an always-on cell, and where is it physically placed?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
An always-on cell is a buffer, inverter or similar cell that keeps working while the domain around it is off, because it has a backup supply pin tied to an always-on rail. It is placed inside the shutdown voltage area, on nets that must stay alive there. Its secondary power pin is routed to a nearby always-on strap.
Technical Explanation
- An always-on cell has a backup power pin besides its primary pins, and the backup supply stays on during shutdown.
- It carries nets that must stay live inside a shutdown area: isolation enables, save and restore, switch control and feedthroughs.
- It sits in the normal rows of the shutdown voltage area, next to the logic it serves.
- Its secondary PG pin connects to an always-on strap, so the placer keeps it close to that strap.
- ICC2 only does always-on optimisation if the library has buffers and inverters marked with the always_on attribute.
- Some always-on cells have only a backup pin, connect straight to the secondary strap through vias, and need well breaker cells.
- Cell names such as AO_BUF_X2 on this page are illustrative.
Common Mistake
The Trap: Assuming an always-on cell must be placed outside the shutdown area.
- Signals crossing that area then take long detours, or engineers insert regular buffers on the switched rail that die at shutdown.
- The other slip is placing it right but leaving its secondary PG pin unrouted, so it has no power during shutdown.
Follow-up Question & Model Response
"What goes wrong if a dual-rail always-on buffer is placed far from its secondary strap?"
Candidate Model Response: The secondary PG route from the cell to the strap gets long. The ICC2 MV guide warns that such routes can suffer too much IR drop or electromigration. Secondary PG placement constraints tell the placer where the straps are so dual-rail cells stay near them. Dual-rail cells also get priority over single-rail cells for those spots. A backup pin left floating in the PG netlist shows up in check_lp (VCLP) under PG_PIN_UNCONN.
Practical Example
Design Scenario: (illustrative) In MYCHIP, U_PC drives the save net across the PD_COP voltage area to retention flops 500 µm away. ICC2 inserts two AO_BUF_X2 cells in PD_COP rows. Their primary pins sit on VDD1p0_SW and their backup pins connect to a VDD1p0 strap running every 60 µm. When PD_COP is off, the two buffers still drive save. If a strap were missing near one buffer, its secondary route would grow, and so would its IR drop.
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