Level 1: Foundations

Beginner Low Power Interview Questions

Build a clear foundation in power components, domains, supplies, isolation, level shifting, retention, switches, and UPF.

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What to practise at this level

Build a clear foundation in power components, domains, supplies, isolation, level shifting, retention, switches, and UPF.

01 Why is low-power design necessary in modern chip design?Beginner: Power now limits what a chip can do as much as timing and area do. Battery life, heat the package can remove, and leakage that grows at every smaller node all cap performance, so power has to be planned from RTL onward. Each of those limits shows up as a concrete physical-design task: domains, switches, multi-Vt mixes and a stronger power grid.
02 What is the difference between dynamic power and leakage (static) power?Beginner: Dynamic power flows only when nodes switch: every 0-to-1 transition charges a capacitance from the supply. Leakage power flows all the time the transistors are powered, even with the clock stopped, because off transistors are never fully off. You cut dynamic power by switching less or at lower voltage, and leakage by using higher-Vt cells or removing the supply.
03 What are the three components of dynamic power dissipation in a CMOS gate?Beginner: The three components are switching power, short-circuit power, and glitch power. Switching power charges the load capacitance on every useful transition, short-circuit power flows while both transistors conduct during a slow input edge, and glitch power comes from extra, unwanted transitions before a node settles. In libraries, the short-circuit part is usually modelled inside the cell as internal power.
04 What causes leakage power in a CMOS transistor?Beginner: An off transistor still conducts a small current through three main paths: subthreshold conduction under the channel, tunnelling through the gate oxide, and reverse-biased junction leakage including GIDL. At advanced nodes subthreshold leakage dominates, because threshold voltages were lowered to keep gates fast. Gate leakage was brought down by high-k metal gates, so it matters less than it once did.
05 What is the trade-off between high-threshold-voltage (HVt) and low-threshold-voltage (LVt) cells?Beginner: LVT cells switch faster because they turn on at a lower gate voltage, but they leak much more when off. HVT cells leak far less but are slower. You use HVT everywhere timing allows and spend LVT only on paths that cannot meet timing otherwise.
06 How does temperature affect leakage power?Beginner: Leakage rises steeply with temperature, because heat lowers the threshold voltage and increases subthreshold and junction current. Illustratively, a block can leak several times more at 125 °C than at 25 °C. That creates a feedback loop: more leakage makes more heat, which makes more leakage.
07 How does process corner (fast/typical/slow) affect power?Beginner: A fast (FF) corner has lower thresholds and stronger transistors, so it has the worst leakage and runs fastest. A slow (SS) corner has the least leakage but the worst setup timing. So the corner that fails timing is rarely the corner that fails power, and you sign off each at its own worst case.
08 What is the "worst-case power corner" used for power signoff?Beginner: For leakage, the worst case is fast process, maximum voltage and maximum junction temperature, because every one of those raises off-current. For dynamic and peak power, the worst case is maximum voltage with the activity of the busiest real mode. Average battery power is usually reported separately at typical conditions with realistic use-case activity.
09 Why does reducing supply voltage (Vdd) help reduce power, and what is the trade-off?Beginner: Dynamic power scales with the square of supply voltage, so a small voltage cut gives a large power saving, and leakage drops too. The price is speed: gate delay rises as Vdd gets closer to the threshold voltage. Below a floor set by Vt and memory stability, the logic slows badly or stops working reliably.
10 What is a power domain?Beginner: A power domain is a group of instances that are treated as one unit for power management, and that normally share one primary supply. Everything in it powers up, powers down or changes voltage together. The domain is also where you attach the strategies for its boundary: isolation, level shifting and retention.
11 Can you give an example of a chip with multiple power domains?Beginner: A phone SoC is the classic example: the big CPU cluster, the GPU and the modem each sit in their own switchable domain, and a small always-on domain keeps the power controller, real-time clock and wake-up logic alive. Each switchable domain turns off or scales its voltage based on what the phone is doing. The always-on domain decides when they come back.
12 What are the different states a power domain can be in (fixed voltage, switchable, DVS, DFS, DVFS)?Beginner: A domain can be fixed (one voltage, always on), switchable (power can be cut), DVS (voltage changes at run time), DFS (clock frequency changes) or DVFS (voltage and frequency change together). Each type adds its own hardware and verification. The more a domain can change, the more crossings and states you have to check.
13 What are supply nets and supply ports in UPF?Beginner: A supply port is the entry point where power crosses a boundary, such as a chip pad or a block pin. A supply net is the wire that carries that power inside a scope, and connecting a net to a port joins them. UPF builds the power network from these two objects before any domain can use a supply.
14 What is a supply set in UPF?Beginner: A supply set is a named bundle of supply functions, power and ground, plus optional bias functions, that together form one complete power source. Instead of naming each net, you hand a domain or strategy the bundle. You can refer to its functions, such as SS_COP.power, and bind them to real nets now or later.
15 What is the "primary power net" of a power domain?Beginner: The primary power and ground of a domain are the default supply for every cell in it: any instance without an explicit supply connection gets them automatically. In IEEE 1801-2015 you give them as the domain's primary supply set; older UPF named the nets directly. Physically, they are the rails that the standard-cell rows in that domain sit on.
16 What is the difference between primary power and backup (retention) power?Beginner: Primary power runs the whole domain and is the supply that turns off when the domain shuts down. Backup, or retention, power is a separate always-on supply that keeps a small part of each retention flop alive, so the saved bit survives. In Liberty the two show up as different pin roles on the same cell: primary_power and backup_power.
17 What is the difference between a switched power supply and an always-on power supply?Beginner: A switched supply sits behind a power switch and disappears when the switch opens; it is often called the virtual rail. An always-on supply comes straight from the regulator and never turns off during operation. The switch, its control path, isolation cells and retention latches must run on the always-on supply, because they have to work while the switched rail is off.
18 What does "power-up" and "power-down" mean for a domain?Beginner: Power-down means the power controller opens the switch in front of a domain so its rail decays to 0 V and the logic inside stops leaking. Power-up means closing the switch again, letting the rail ramp back to full voltage, and bringing the logic back to a known state before it is used. Both are ordered sequences run by always-on logic, not a single flip of a switch.
19 What is a power state table?Beginner: A power state table (PST) lists the combinations of supply values the chip is allowed to be in at the same time. Each row is one legal mode, such as all domains on, or the GPU off while the CPU runs at low voltage. Implementation and checking tools use it to decide which crossings need level shifters and isolation.
20 What is a "valid" vs an "invalid" signal, and why does this matter when a domain shuts down?Beginner: A valid signal sits at a clean logic 0 or logic 1, driven by a powered gate. When a domain shuts down, its outputs are no longer driven, so they float or settle somewhere between the rails. That invalid value can waste power in the receiving gate and make always-on logic act on garbage.
21 What is an isolation cell and why is it needed?Beginner: An isolation cell is a small gate on a signal leaving a domain that can switch off, and it forces that signal to a known value while the domain is off. It exists because an unpowered driver leaves the net floating, and the always-on receiver would otherwise read garbage and leak current. The cell is powered from a supply that stays on and is controlled by an enable from always-on logic.
22 What is the difference between an AND-type and an OR-type isolation cell (clamp value)?Beginner: An AND-type isolation cell clamps its output to 0, and an OR-type isolation cell clamps its output to 1. The AND gate clamps when its enable input goes low, and the OR gate clamps when its enable goes high. In UPF you choose between them with the clamp value of the isolation strategy, and the tool maps that to the right cell.
23 What is a level shifter and why is it needed?Beginner: A level shifter is a cell that converts a signal from the voltage swing of one domain to the swing of another. It is needed because a logic 1 from a lower-voltage domain is not high enough to turn off the PMOS of a gate on a higher supply. Without it the receiver leaks crowbar current and may switch late or read the wrong value.
24 What is the difference between a low-to-high and a high-to-low voltage crossing?Beginner: A low-to-high crossing goes from a lower-voltage domain into a higher one, and a high-to-low crossing goes the other way. Low-to-high needs a level shifter, because the weak input cannot turn off the receiver PMOS. High-to-low often works without one, so it depends on the library and the threshold you set.
25 What is an enable level shifter (ELS)?Beginner: An enable level shifter is one cell that does both jobs at a boundary: it shifts the voltage while the source is on and clamps the output while the source is off. You use it where a signal leaves a switchable domain and also changes voltage. It saves area and delay compared with a separate isolation cell plus level shifter.
26 What is a power switch and what does it do?Beginner: A power switch is a large transistor cell placed between a real supply rail and a domain, so the power controller can disconnect that domain. When it is off, the domain's rail collapses and both dynamic and leakage power in the domain drop to near zero. You pay for it with area, a small IR drop through the switch, and wake-up time.
27 What is the difference between a header switch and a footer switch?Beginner: A header switch is a PMOS transistor between the real power rail VDD and the domain's virtual power rail. A footer switch is an NMOS transistor between the domain's virtual ground and the real ground VSS. Both cut the same current path, just from different sides.
28 What is a mother-daughter power switch configuration, and why would you stage the switch turn-on?Beginner: A mother-daughter configuration pairs a weak switch transistor with a strong one on the same rail. The weak one turns on first and charges the domain slowly, and the strong one turns on after to give full current with low resistance. Staging this way keeps the in-rush current peak small, so neighbours on the same supply do not see a voltage dip.
29 What is a "virtual rail," and how is it different from the primary supply?Beginner: A virtual rail is the supply net on the output side of a power switch, and it only exists behind that switch. The real supply feeds the switch and is always driven, while the virtual rail goes to 0 V whenever the switch is off. For a switchable domain, the virtual rail is the domain's primary supply.
30 What is a switched ground net, and how does it relate to a footer switch?Beginner: A switched ground net is the ground rail of a domain that reaches real ground only through a footer switch. The footer is an NMOS transistor between that net, often called VVSS, and the real VSS. When the footer opens, VVSS is cut off from VSS and drifts up toward VDD, so the domain stops conducting.
31 What is an isolation control signal, and why must it stay "alive" even when a domain shuts down?Beginner: The isolation control signal is the enable that tells isolation cells when to clamp. It must stay driven while the protected domain is off, because the clamp has to hold for the entire shutdown. So it comes from always-on logic and is buffered only by always-on cells along its whole route.
32 What is a retention signal (save/restore), and why is it needed?Beginner: Retention signals are the control inputs, usually SAVE and RESTORE, that tell retention registers when to copy their state into a backup latch and when to copy it back. The always-on power controller drives them around each power-down and wake-up. Without them the domain loses its state and must fully reset and reinitialise on every wake-up, which costs time, energy and a software setup pass.
33 What does "save and restore" mean for a retention register?Beginner: Save means copying the main flop's value into a small shadow latch that stays powered. Restore means copying that value back into the main flop after power returns. Between the two, the main flop is off and only the shadow latch holds the state.
34 What is an always-on cell, and where is it physically placed?Beginner: An always-on cell is a buffer, inverter or similar cell that keeps working while the domain around it is off, because it has a backup supply pin tied to an always-on rail. It is placed inside the shutdown voltage area, on nets that must stay alive there. Its secondary power pin is routed to a nearby always-on strap.
35 What is "power intent," and why do we need a separate language (UPF) to describe it?Beginner: Power intent is the description of how a chip is powered: which logic sits on which supply, which blocks can switch off, and what each domain boundary needs to stay safe. It lives in a separate UPF (IEEE 1801) file because RTL describes function, not supplies, and one file read by synthesis, P&R, timing and simulation keeps every tool working from the same power plan.
36 What does the create_power_domain command do in UPF?Beginner: `create_power_domain` (UPF) names a power domain and lists the instances that belong to it, so every cell in those instances shares one primary supply and one set of strategies. The domain is created in the current scope, and every instance in the design must end up in exactly one domain.
37 What is multivoltage design?Beginner: Multivoltage design runs different blocks of one die at different supply voltages. Blocks that need speed get a higher voltage, and everything else runs lower to save power, since dynamic power scales with the square of the voltage.
38 What is a voltage crossing between power domains?Beginner: A voltage crossing is a net whose driver and receiver sit in power domains at different voltages. Every domain crossing raises two questions: does the signal need a level shifter, and does it need isolation because the driver can be off while the receiver is on?
39 What is a basic low-power verification check (e.g. check_mv_design), and what is it looking for?Beginner: `check_mv_design` (ICC2) checks the netlist against the UPF and reports electrical mistakes. By default it looks for missing level shifters and isolation cells, strategies that disagree with the power state table, and supply and PG-pin rule problems. PG-net and PG-connection checks, such as supply nets without a voltage, run only when you add `-pg_netlist` or `-all`.
40 Can you describe a basic low-power implementation mistake, like a missing isolation cell?Beginner: A missing isolation cell leaves an output of a switchable domain driving always-on logic with nothing to hold it when the source powers down. The receiver sees a floating value, which causes crowbar current and random logic behaviour only when the domain actually turns off.
41 What is adiabatic logic, and how does it fundamentally change how dynamic power is dissipated compared to standard CMOS switching?Beginner: Adiabatic logic charges each load slowly from a ramping supply, called a power clock, instead of a fixed step. If the ramp is much slower than the RC time constant, most of the energy is returned to the supply rather than burned as heat. It is rare in standard-cell ASIC flows because it needs special cells, multi-phase power clocks and low speed.
42 What is battery-aware design, and how does Peukert's law change how you evaluate a low-power architecture?Beginner: Battery-aware design judges a chip by the shape of its current draw, not just its average power. Peukert's law says a battery delivers less total charge when drained at a higher current, so a bursty design can run out sooner than a smooth one with the same average.
43 What is DVFS, and what is the safe sequencing rule when raising or lowering voltage and frequency together?Beginner: DVFS (dynamic voltage and frequency scaling) changes a domain's supply voltage and clock frequency at run time to match the workload. The safe rule is: raise voltage before frequency when going up, and lower frequency before voltage when going down, so the logic is never clocked faster than its current voltage supports.
44 What is bus-invert encoding, and how does it reduce switching activity on a wide data bus?Beginner: Bus-invert encoding sends either the data word or its complement, whichever flips fewer wires compared with the value already on the bus. One extra flag wire tells the receiver which version it got, capping toggles at about half the bus width per transfer. The saving is largest on long, busy buses carrying random data.
45 What is Gray code addressing, and why does it reduce switching power compared to binary counting?Beginner: In Gray code, consecutive values differ in exactly one bit, while a binary increment can flip many bits at once. For counters and address buses that step sequentially, that keeps toggles to one per step and cuts switching power, as long as the value really does move by one each time.
46 What is the stack effect (transistor stacking), and how does it reduce subthreshold leakage in an idle logic gate?Beginner: The stack effect is the drop in subthreshold leakage when two or more off transistors sit in series. The node between them rises to a small positive voltage, which pushes the upper transistor harder off and cuts the voltage across the lower one, so the stack leaks much less than a single off transistor.
47 What is operand isolation, and how does it differ from clock gating for saving power in idle datapath logic?Beginner: Operand isolation holds the inputs of a combinational block, such as a multiplier, at a constant when its result is not needed, so its internal logic stops switching. Clock gating stops the clock to registers instead. The two are complementary: one saves datapath power, the other saves clock and register power.
48 What is a voltage area, and how is it different from a power domain?Beginner: A power domain is a logical group of instances in the UPF that share a primary supply. A voltage area is the physical region in the floorplan where those cells may be placed. Usually one domain maps to one voltage area, but several domains with the same primary supply can share one.
49 What is a secondary power pin, and which cells have one?Beginner: A secondary power pin is a second supply pin on a dual-rail cell, fed from a strap other than the row rail it sits on. Always-on buffers, isolation cells, level shifters, retention flops and always-on tie cells use one because they must see a supply the row does not provide.
50 What is switching activity (SAIF/VCD), and why does power analysis need it?Beginner: Switching activity is how often each net toggles and how long it sits at 1. Dynamic power depends directly on it, so the power number is only as good as the activity you feed in: SAIF gives toggle counts, VCD gives full waveforms, and without either the tool falls back to default activity.

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