What does "save and restore" mean for a retention register?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
Save means copying the main flop's value into a small shadow latch that stays powered. Restore means copying that value back into the main flop after power returns. Between the two, the main flop is off and only the shadow latch holds the state.
Technical Explanation
- A retention register is a normal flop or latch plus a state-saving latch, often called a shadow or balloon latch, with its own supply.
- The main flop uses fast low-Vt transistors on the switched primary supply.
- The shadow latch uses high-Vt transistors on an always-on backup supply, so it leaks very little.
- On save, the flop's Q is copied into the shadow latch; the switch can then turn off.
- On restore, after the rail is back and settled, the latch value is loaded into the main flop before clocks restart.
- In the balloon style the shadow latch sits off the main data path, so it adds little delay at speed.
- In UPF,
-retention_supplyonset_retention(UPF) names the latch supply. Legacy form (still accepted by ICC2/PT):-retention_power_net.
Common Mistake
The Trap: Putting the shadow latch on the same switched rail as the main flop, for example by naming the primary supply as the retention supply.
- The saved value disappears with the rail, and the flop wakes up at an unknown value.
- Power-aware simulation shows the flop coming back as X, which is the cue to check the retention supply in the UPF.
Follow-up Question & Model Response
"Can the shadow latch run at a lower voltage than the main flop?"
Candidate Model Response: Yes. It only holds a static value and never switches at speed, so some designs run it from a lower backup rail to cut its leakage further. The limit is the lowest voltage at which the latch still holds data reliably, which the library characterises. Whatever rail you pick, it must stay on for the whole time the primary supply is off.
Practical Example
Design Scenario: (illustrative) PD_COP has 256 retention flops. Their main flops run on VDD1p0_SW, and their shadow latches run on VDD1p0. U_PC stops the clock and pulses save, the switches turn off, and the 256 shadow latches hold the state. On wake-up, VDD1p0_SW returns to 1.0 V and U_PC pulses restore. Each flop now holds exactly what it held before sleep. The cost: every retention flop is larger than a plain flop, and the 256 shadow latches keep leaking from VDD1p0 while PD_COP sleeps.
Low-Power & UPF Handbook
Master Low-Power VLSI & Multivoltage Design
Read the complete low-power guide library covering power domains, level shifters, isolation clamps, state retention, and UPF signoff verification.
Offline PDF Bundle
Want all 1109 questions offline?
Get the complete 4-book PDF bundle (PnR, STA, MMMC, Low Power) with a clickable table of contents - no ads, no internet needed.
Continue practising