What is a delay corner?
From PDVerse MMMC Interview Masterclass, part of the pdVerse Mentor Series
Direct answer
A delay corner is the binding of a library set (cell timing physics) with an RC corner (wire parasitic physics), providing the complete physical data required to calculate cell and interconnect delays along a timing path.
Mentor explanation
A delay corner combines cell timing physics and wire parasitic physics into one physical object.
Key terms
create_delay_corner(Innovus) — binds-library_setand-rc_cornertogether in one definition.- Early/late delay corner — pairs min-delay and max-delay data to model on-chip variation between clock and data paths.
- Physical purity — a delay corner contains only physical parameters; it has no concept of clocks, modes, or timing exceptions.
A delay corner only knows how long cells and wires take to switch. Pairing that physical capability with a constraint mode produces an active analysis view.
Practical example
Delay Corner Definition:
# Pairing SSG cell models with RCmax wire parasitics for Setup analysis
create_delay_corner -name dc_ss_125c_rcmax \
-library_set libset_ss_125c \
-rc_corner rccorn_rcmax
# Pairing FFG cell models with RCmin wire parasitics for Hold analysis
create_delay_corner -name dc_ff_m40c_rcmin \
-library_set libset_ff_m40c \
-rc_corner rccorn_rcminInterview trap
Thinking a delay corner contains clock definitions or false paths. It is purely physical; behavioral constraints come exclusively from the constraint mode it is paired with.
Key takeaways
- A Delay Corner unifies cell timing (Library Set) and wire parasitics (RC Corner).
- It represents the physical reality of the chip independent of operational mode.
- Pairing a Delay Corner with a Constraint Mode creates an Analysis View.
Self-check: can you answer this aloud?
Try a 45-second answer using this structure:
- State the direct answer.
- Explain the timing or physical reason.
- Name one caveat.
- Say how you would verify it in a real flow.
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