VLSI STA & Timing Signoff Masterclass, 40 questions
Master MMMC interview reasoning through 40 complete answers covering foundations, practical debugging, and signoff decisions.
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A mode is what the chip is doing at a given moment — functional execution, scan shift, scan capture, memory BIST, or low-power standby — on the exact same physical netlist. Nothing about the silicon changes between modes; only which clocks are toggling, which control pins are pinned to constants, and which timing constraints apply.
Mode answers "what is the chip doing?" Corner answers "under what physical conditions?" They are two completely independent, orthogonal axes, and an analysis view (or scenario) is what you get when you pick one of each.
A constraint mode is a named container that bundles together everything SDC-related for one behavioral mode — clock definitions, I/O delays, case analysis values, and timing exceptions — so the tool can reference that mode's constraints as a single reusable object.
Different operating modes require mutually exclusive case analysis values on the same control pins, conflicting clock relationships, and mode-specific exceptions. Packing all of that into one giant monolithic SDC produces contradictory constraints, unroutable paths, and false path leakage.
PVT stands for Process, Voltage, and Temperature — the three physical variables that govern transistor switching speed in manufactured silicon. Worst-case timing signoff must analyze these variables simultaneously across their operating extremes.
A standard cell does not have a single fixed delay because delay depends dynamically on the specific electrical operating conditions it experiences: its PVT corner, its input transition time (input slew), and the capacitive load on its output pin (C_load).
A timing library (Liberty .lib / compiled .db) is the SPICE-characterized rulebook for every cell in a library at one specific PVT point — specifying its logic function, pin capacitances, propagation delays, output transition tables, sequential timing checks (setup, hold, recovery, removal), and power.
Input slew is the transition time required for an input voltage edge to ramp between logic thresholds (e.g. 10%–90% or 20%–80%). Slower input slew keeps internal transistors in their high-resistance transition region longer, delaying switching and degrading output transition time.
Output load is the total capacitance a cell's output pin must charge or discharge — the sum of all downstream receiver input pin capacitances plus routed wire capacitance. Higher capacitive load requires more time to charge (I = C·dV/dt), directly increasing propagation delay and slowing output slew.
Parasitics are the unintended electrical properties inherent in physical metal wires: series resistance (R), ground capacitance (C_gnd), and lateral coupling capacitance to neighboring signal wires (C_c). They convert ideal schematic connections into distributed RC delay networks.
A routed wire has distributed resistance and capacitance that scale delay quadratically (t ∝ L²) for unbuffered lines, degrades signal transition times like a low-pass filter, adds via resistance, and exposes signals to crosstalk noise from adjacent switching neighbors.
SPEF (Standard Parasitic Exchange Format, IEEE 1481) is the standard ASCII file format that transfers extracted wire resistance, ground capacitance, and cross-coupling capacitance from physical extraction tools (StarRC, Quantus) into STA engines (PrimeTime, Tempus).
An RC corner is a physical interconnect extraction condition modeling the manufacturing variations in metal wire thickness, width, and inter-wire spacing (CMP polishing, etching tolerances), independent of transistor process variations.
A library set is a named bundle of timing libraries (.lib files) representing all standard cells, memory macros, IO pads, and analog IP characterized at the exact same PVT condition, ensuring electrical consistency across the entire design.
A delay corner is the binding of a library set (cell timing physics) with an RC corner (wire parasitic physics), providing the complete physical data required to calculate cell and interconnect delays along a timing path.
No. A delay corner is purely physical data (library set + RC corner). It only becomes a setup view or a hold view when paired with a constraint mode and explicitly activated for that check type via tool commands.
An analysis view (called a "scenario" in Synopsys tools) is the complete unit of static timing analysis — binding one constraint mode (logical intent) to one delay corner (physical environment) to form a timing graph against which slack is computed.
Setup timing is a maximum-delay check verifying that data arrives before the next clock edge (N+1). Hold timing is a minimum-delay check verifying that data remains stable long enough not to corrupt data captured on the current clock edge (N).
An MMMC timing run requires five core file types: the gate-level netlist (.v), characterized Liberty timing libraries (.lib/.db) for all PVT corners, mode-specific SDC constraint files, extracted parasitic files (SPEF) for all RC corners, and an MMMC configuration script (.tcl).
Level 2: Construction & Debugging
A path's physical gates and wires are identical across views, but its operational frequency (mode), cell switching speeds (PVT corner), wire delays (RC corner), and active timing exceptions differ between views, producing different arrival and required times in each view.
Yes. Reusing one constraint mode across multiple delay corners is the standard MMMC methodology. It guarantees that functional timing intent (clock frequencies, I/O budgets, exceptions) remains identical across all physical process and environmental corners.
Yes. A delay corner is purely physical (a specific PVT and RC condition). Physical transistor and wire physics remain identical regardless of whether the chip is running functional data, scan test patterns, or BIST.
"SS means setup, FF means hold" is unsafe in advanced FinFET nodes because temperature inversion can make cold (-40°C) slower than hot (125°C) for setup, while gate-dominated and wire-dominated paths have different worst RC corners.
Creating an analysis view (`create_analysis_view`) registers the view definition in the database without evaluating timing. Activating it (`set_analysis_view -setup {...} -hold {...}`) instructs the timing engine to build the timing graph, compute slack, and optimize against that view.
An unactivated view is completely ignored by the timing engine — no slack is calculated, no paths are checked, and no violations are reported. It creates a dangerous silent escape because summary reports show zero violations, mimicking a clean signoff.
To debug an unexpected timing violation, start by validating constraint integrity (`check_timing`) to rule out false paths or clock definition errors, then inspect a full-clock expanded timing report (`report_timing -path_type full_clock_expanded -input_pins -nets -capacitance -transition_time`) to isolate whether the root cause is clock skew, high cell delay, or wire RC/crosstalk.
Cadence (Innovus/Tempus) and Synopsys (ICC2/PrimeTime) represent the same concept (mode × corner), but structure it differently: Cadence uses an explicit 4-tier assembly (`library_set` + `rc_corner` → `delay_corner`, paired with `constraint_mode` → `analysis_view`), while Synopsys combines scenario SDC and corner operating conditions directly inside `create_scenario`.
Pre-route timing relies on estimated wire lengths (global routing or virtual routes) with ideal slews and zero crosstalk. Detailed routing introduces actual metal layer assignments, via resistance stacks, detour routing around congestion, and signal integrity crosstalk coupling from switching neighbors.
Scenario explosion occurs when multiplying multiple modes by many physical corners produces hundreds of analysis views (e.g. 10 modes × 15 corners = 150 views), exhausting memory and bloating PnR runtimes. The solution is dominant scenario pruning during PnR, expanding to the full matrix for final signoff.
Level 4: Signoff Reasoning
A setup ECO fixes slow-corner timing by upsizing cells or swapping to lower threshold-voltage (LVT/ULVT) cells. Because that physical silicon change applies across all views, it accelerates data arrival in the fast hold corners (FF/-40°C), creating new hold violations.
ICC2 uses streamlined delay calculation approximations and simplified modeling to maintain fast PnR optimization turnaround. PrimeTime is the golden signoff timer that uses exhaustive CCS/ECSM current-source models, full PrimeTime-SI crosstalk analysis, and path-based analysis (PBA).
When identical netlists yield different timing results, first compare the environment and input files: diff the SDC constraints, check SPEF annotation coverage and corner settings (`report_annotated_parasitics`), verify library release versions, and audit tool variables and OCV derates (`report_ocvm`).
No. A clean `read_spef` command only confirms syntax validity. If net or instance names in the SPEF do not match the gate netlist (e.g. hierarchy delimiter mismatches or renamed ECO nets), the tool silently ignores the parasitics and defaults to zero wire delay.
Cell delay depends on output capacitive load ($C_{load}$) and input transition time (slew). A higher RC corner increases the capacitive load on the cell's output (slowing it down) and degrades interconnect slew, delivering a slower transition to all downstream receiver cells.
Different analysis views have different critical paths. The worst-WNS scenario may constrain the high-speed functional datapath, while another scenario with lower WNS may be the only view that exercises scan test chains, asynchronous interfaces, or low-power retention paths.
GBA (Graph-Based Analysis) is conservative and pessimistic: at multi-input gates, it assumes worst-case input slew across all inputs propagates to the output, compounding pessimism down the tree. PBA (Path-Based Analysis) re-evaluates the path using the exact propagating slew. PBA is trusted for signoff because it removes artificial mathematical pessimism.
Enabling Signal Integrity (SI) analysis introduces crosstalk delta delays ($Delta t$) caused by switching aggressor nets. Corners with fast switching slews (FF) or lower supply voltages can experience severe crosstalk slowdown or speedup that changes which corner exhibits the worst slack.
The timing engine uses the actual bound physical objects (the linked `library_set` and `rc_corner`), completely ignoring the string name of the view. A view named `FUNC_SS_RCMAX` that points to an FF library will evaluate fast-process physics, silently producing invalid setup results.
As signoff lead, ask for the complete signoff audit evidence: (1) Was the full signoff matrix active (all modes × all corners)? (2) Is `check_timing` clean with zero unconstrained endpoints? (3) Is parasitic annotation 100% verified via `report_annotated_parasitics`? (4) Was PrimeTime SI crosstalk enabled? (5) Were PBA reports run on near-critical paths? (6) Are min-pulse-width and max-transition design rules clean?