Level 1: Foundations

Beginner MMMC Interview Questions

Build a precise vocabulary for modes, corners, libraries, parasitics, delay corners, analysis views, setup, and hold.

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What to practise at this level

Aim to explain each building block without mixing behavioral intent with physical conditions. Your answer should stay simple while still naming the caveat that makes it signoff-safe.

  1. 01 What is MMMC, and why can't one timing run tell the whole story?Beginner: MMMC (Multi-Mode Multi-Corner) is the industry standard methodology for verifying static timing across every combination of what the chip is doing (operational mode) and what condition the silicon is in (physical PVT and RC corner). You sign off a chip only once every single combination passes timing cleanly.
  2. 02 What is a "mode," in plain terms?Beginner: A mode is what the chip is doing at a given moment — functional execution, scan shift, scan capture, memory BIST, or low-power standby — on the exact same physical netlist. Nothing about the silicon changes between modes; only which clocks are toggling, which control pins are pinned to constants, and which timing constraints apply.
  3. 03 What's the actual difference between a "mode" and a "corner"?Beginner: Mode answers "what is the chip doing?" Corner answers "under what physical conditions?" They are two completely independent, orthogonal axes, and an analysis view (or scenario) is what you get when you pick one of each.
  4. 04 What is a constraint mode?Beginner: A constraint mode is a named container that bundles together everything SDC-related for one behavioral mode — clock definitions, I/O delays, case analysis values, and timing exceptions — so the tool can reference that mode's constraints as a single reusable object.
  5. 05 Why can't we just use one SDC file for every operating condition?Beginner: Different operating modes require mutually exclusive case analysis values on the same control pins, conflicting clock relationships, and mode-specific exceptions. Packing all of that into one giant monolithic SDC produces contradictory constraints, unroutable paths, and false path leakage.
  6. 06 What does PVT actually stand for, and what does each letter mean?Beginner: PVT stands for Process, Voltage, and Temperature — the three physical variables that govern transistor switching speed in manufactured silicon. Worst-case timing signoff must analyze these variables simultaneously across their operating extremes.
  7. 07 Why doesn't a standard cell have just one fixed delay?Beginner: A standard cell does not have a single fixed delay because delay depends dynamically on the specific electrical operating conditions it experiences: its PVT corner, its input transition time (input slew), and the capacitive load on its output pin (C_load).
  8. 08 What is a timing library, really?Beginner: A timing library (Liberty .lib / compiled .db) is the SPICE-characterized rulebook for every cell in a library at one specific PVT point — specifying its logic function, pin capacitances, propagation delays, output transition tables, sequential timing checks (setup, hold, recovery, removal), and power.
  9. 09 What is input slew, and why does it change a cell's delay?Beginner: Input slew is the transition time required for an input voltage edge to ramp between logic thresholds (e.g. 10%–90% or 20%–80%). Slower input slew keeps internal transistors in their high-resistance transition region longer, delaying switching and degrading output transition time.
  10. 10 What is output load, and why does it affect delay?Beginner: Output load is the total capacitance a cell's output pin must charge or discharge — the sum of all downstream receiver input pin capacitances plus routed wire capacitance. Higher capacitive load requires more time to charge (I = C·dV/dt), directly increasing propagation delay and slowing output slew.
  11. 11 What are parasitics, in plain language?Beginner: Parasitics are the unintended electrical properties inherent in physical metal wires: series resistance (R), ground capacitance (C_gnd), and lateral coupling capacitance to neighboring signal wires (C_c). They convert ideal schematic connections into distributed RC delay networks.
  12. 12 Why isn't a routed wire just an ideal connection?Beginner: A routed wire has distributed resistance and capacitance that scale delay quadratically (t ∝ L²) for unbuffered lines, degrades signal transition times like a low-pass filter, adds via resistance, and exposes signals to crosstalk noise from adjacent switching neighbors.
  13. 13 What is SPEF, and what does it actually represent?Beginner: SPEF (Standard Parasitic Exchange Format, IEEE 1481) is the standard ASCII file format that transfers extracted wire resistance, ground capacitance, and cross-coupling capacitance from physical extraction tools (StarRC, Quantus) into STA engines (PrimeTime, Tempus).
  14. 14 What is an RC corner?Beginner: An RC corner is a physical interconnect extraction condition modeling the manufacturing variations in metal wire thickness, width, and inter-wire spacing (CMP polishing, etching tolerances), independent of transistor process variations.
  15. 15 What is a library set?Beginner: A library set is a named bundle of timing libraries (.lib files) representing all standard cells, memory macros, IO pads, and analog IP characterized at the exact same PVT condition, ensuring electrical consistency across the entire design.
  16. 16 What is a delay corner?Beginner: A delay corner is the binding of a library set (cell timing physics) with an RC corner (wire parasitic physics), providing the complete physical data required to calculate cell and interconnect delays along a timing path.
  17. 17 Is a delay corner the same thing as a setup view or a hold view?Beginner: No. A delay corner is purely physical data (library set + RC corner). It only becomes a setup view or a hold view when paired with a constraint mode and explicitly activated for that check type via tool commands.
  18. 18 What is an analysis view?Beginner: An analysis view (called a "scenario" in Synopsys tools) is the complete unit of static timing analysis — binding one constraint mode (logical intent) to one delay corner (physical environment) to form a timing graph against which slack is computed.
  19. 19 What is setup timing, and what is hold timing, in plain terms?Beginner: Setup timing is a maximum-delay check verifying that data arrives before the next clock edge (N+1). Hold timing is a minimum-delay check verifying that data remains stable long enough not to corrupt data captured on the current clock edge (N).
  20. 20 What are the major files an MMMC timing run actually needs?Beginner: An MMMC timing run requires five core file types: the gate-level netlist (.v), characterized Liberty timing libraries (.lib/.db) for all PVT corners, mode-specific SDC constraint files, extracted parasitic files (SPEF) for all RC corners, and an MMMC configuration script (.tcl).

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