IntermediateQuestion 3 of 10Source page 11

Can one delay corner be reused across several different modes?

From PDVerse MMMC Interview Masterclass, part of the pdVerse Mentor Series

Direct answer

Yes. A delay corner is purely physical (a specific PVT and RC condition). Physical transistor and wire physics remain identical regardless of whether the chip is running functional data, scan test patterns, or BIST.

Technical Reference DiagramCan one delay corner be reused across several different modes?

Mentor explanation

Delay corners represent physical silicon conditions and are independent of operational modes.

Key terms

  • Physical independence โ€” a gate's delay at SS/0.675V/125ยฐC is identical whether it switches functional logic or scan test patterns.
  • Reuse pattern โ€” dc_ss_125c_rcmax paired with cm_functional creates view 1; the same delay corner paired with cm_scan_shift creates view 2.
  • Memory/runtime benefit โ€” reusing delay corner objects allows tools to share cached library characterization and parasitic data across modes.

Creating duplicate delay corner objects per mode bloats memory and adds unnecessary maintenance overhead.

Practical example

Delay Corner Sharing in Scripting:

# Define the physical Slow-Slow Max-RC Delay Corner once
create_delay_corner -name dc_ss_125c_rcmax -library_set libset_ss -rc_corner rc_max

# Pair with multiple distinct mode constraints
create_analysis_view -name func_setup -constraint_mode cm_func -delay_corner dc_ss_125c_rcmax
create_analysis_view -name scan_setup -constraint_mode cm_scan -delay_corner dc_ss_125c_rcmax
create_analysis_view -name bist_setup -constraint_mode cm_bist -delay_corner dc_ss_125c_rcmax

Interview trap

Creating duplicate delay corner objects per mode (e.g., dc_func_slow and dc_scan_slow). The underlying physics is identical, so one delay corner should be reused across modes.

Key takeaways

  • Delay corners model physical silicon and wire physics, independent of behavioral modes.
  • A single delay corner can be paired with Functional, Scan, and BIST constraint modes.
  • Reusing delay corners optimizes tool memory and keeps parasitic annotation consistent.
Self-check: can you answer this aloud?

Try a 45-second answer using this structure:

  1. State the direct answer.
  2. Explain the timing or physical reason.
  3. Name one caveat.
  4. Say how you would verify it in a real flow.

MMMC Signoff Guide

Explore the full 10-chapter MMMC guide on modes, PVT corners, RC parasitics, analysis views, and correlation between implementation and signoff tools.

Offline PDF Bundle

Want all 1109 questions offline?

Get the complete 4-book PDF bundle (PnR, STA, MMMC, Low Power) with a clickable table of contents - no ads, no internet needed.

See what's inside the bundle
MMMC Timing Signoff Guide โ€” ten chaptersMMMC GuideTen chapters on modes, corners, and scenario setup.