Why inspect constant-driven pins and nets?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
A constant value (a pin permanently tied to logic 0 or logic 1) isn't automatically suspicious — some are completely intentional, like a mode-select strap that's hardwired for this particular chip variant or configuration. But a constant can also be evidence that something went wrong upstream — synthesis optimized away logic it thought was redundant, a clock got accidentally tied off, or an enable signal that should be dynamic got hardcoded because of a missing connection or a constraint bug.
Technical Explanation
- ) and the active operating mode (a signal that's legitimately constant in one mode might be dynamic in another — if your analysis is only looking at one mode, you could miss that).
- "
- If it's not intentional, this is exactly the kind of thing that's cheap to catch now (a quick netlist inspection) and expensive to catch later (a non-functional chip because a critical enable never toggles).
- " — and use the object name plus the active mode to actually answer it.
Visual Verification
Tying pins to VDD/VSS is normal for static mode configuration straps, but tying active clock enables or test controls to constants permanently disables functional circuits.
What To Check
- Warning sign: A large register bank is constant because the wrong case or synthesis mode was used.
- Inspect: Start with one named object in the report and trace it to the netlist, library, or SDC statement that created it.
- Correct: Compare constants with mode intent and synthesis summaries; correct the producing netlist or constraint rather than reconnecting blindly.
Command Checks & Actions
- check_netlist: reports structural connectivity problems
report_case_analysis: shows constants applied for the active mode
Run the commands in order. Each line answers a separate part of the check.
Healthy, Suspicious & Hard-stop Results
- Expected: Constants can be correct mode straps or evidence that logic, a clock, or an enable was optimised away unexpectedly.
- Stop before floorplanning when required logic or timing coverage is missing or unexplained.
Common Mistake
The Trap: Do not assume the check passed just because ICC2 continued. Fix or narrowly justify the named objects, then rerun the same command.
What The Interviewer Is Testing
Be ready to explain why this matters before floorplanning.
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