Why inspect hierarchy before applying SDC?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
SDC commands like create_clock, set_input_delay, or set_false_path all target objects by path โ and those paths only exist if they match what ICC2 actually loaded, not what the RTL author originally wrote. Synthesis routinely renames, flattens, or removes hierarchy: a module boundary that existed in RTL might be gone after optimization, or an instance name might have picked up a synthesis-tool suffix.
Technical Explanation
- If your SDC selector (
get_cells,get_pins,get_ports) references an old path that no longer exists, the command silently matches nothing โ no error, just an empty collection โ and that constraint never gets applied. - The design ends up underconstrained without any obvious warning: paths that should have been false-pathed or given multicycle treatment get analyzed as ordinary single-cycle paths, and you find out only when timing numbers look wrong or too good.
- The fix is simple discipline: run
report_hierarchy/ inspectreport_designright after import, before sourcing SDC, so you know the real object namespace you're targeting. - This is exactly the same failure mode described elsewhere for library and unit mismatches โ the tool interpreted something differently than you assumed, and the only defense is checking what it actually loaded before trusting downstream numbers.
Visual Verification
Post-synthesis boundary optimizations and hierarchy flattening alter instance names; SDC constraints must reference verified post-synthesis object paths to avoid dropping timing constraints.
What To Check
- Warning sign: Constraints target pre-synthesis paths or a renamed block and resolve to nothing.
- Inspect: Start with one named object in the report and trace it to the netlist, library, or SDC statement that created it.
- Correct: Update the constraint producer's mapping or handoff for the real netlist; avoid broad wildcards as a shortcut.
Command Checks & Actions
- get_cells -hierarchical *: selects design cells
- current_block: confirms the active design block
Run the commands in order. Each line answers a separate part of the check.
Healthy, Suspicious & Hard-stop Results
- Expected: SDC object paths depend on the post-synthesis hierarchy and naming that ICC2 actually loaded.
- Stop before floorplanning when required logic or timing coverage is missing or unexplained.
Common Mistake
The Trap: Do not assume the check passed just because ICC2 continued. Fix or narrowly justify the named objects, then rerun the same command.
What The Interviewer Is Testing
Be ready to explain why this matters before floorplanning.
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