What makes a generated clock different from a primary clock?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
A primary clock is the true starting point of your timing reference — it begins at a real design source, usually an input port, and its period and waveform define the base time reference that everything downstream gets measured against. A generated clock, by contrast, doesn't originate independently — it's derived from a master clock through actual logic in your design, like a clock divider or a mode-select MUX, and its timing characteristics (period, phase, edges) come from that master-source relationship, not from a fresh, independent definition.
Technical Explanation
- The key distinction to hold onto: a primary clock is declared as the reference; a generated clock is declared as a function of another clock plus real circuit behavior — get the master/source relationship wrong and every downstream timing number for that clock domain becomes meaningless.
- Practically, this means when you declare a generated clock in SDC, you must correctly specify its master clock, its source pin, and the actual divide/multiply/edge relationship the real logic implements — the SDC declaration has to match what the netlist actually does, not what you intended it to do.
- A generated clock definition that doesn't correspond to real traceable logic (no real divider, no real MUX path) is a red flag — the tool will accept the syntax, but the resulting timing analysis is disconnected from reality.
Visual Verification
Generated clocks represent internal clock waveforms derived from a master clock via dividers, multipliers, or clock gates, maintaining phase and latency relationships in static timing analysis.
What To Check
- Warning sign: The generated clock exists by name but has the wrong source pin or divide relationship.
- Inspect: Start with one named object in the report and trace it to the netlist, library, or SDC statement that created it.
- Correct: Correct the source/master and transformation in the SDC, then prove a valid path to representative sinks.
Command Checks & Actions
- report_clocks: shows clock definitions and relationships
check_timing-include {generated_clock no_clock}: finds missing or inconsistent timing setup
Run the commands in order. Each line answers a separate part of the check.
Healthy, Suspicious & Hard-stop Results
- Expected: A generated clock derives its frequency, phase, or edges from a master/source relationship in the implemented logic.
- Stop before floorplanning when required logic or timing coverage is missing or unexplained.
Common Mistake
The Trap: Do not assume the check passed just because ICC2 continued. Fix or narrowly justify the named objects, then rerun the same command.
What The Interviewer Is Testing
Be ready to explain why this matters before floorplanning.
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