What must be checked for a primary clock?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
A primary clock originates at a real design source, typically an input port — it's not derived from any other clock in the design. Verification means checking its source object and name are correct, its period and waveform are as intended, and that it's visible in the right modes.
Technical Explanation
- Just as important: confirm its reach — does it actually arrive at every sequential clock pin it's supposed to, or did some register get missed and end up unclocked in the constraint model.
Visual Verification
Primary clocks establish the master time base at design boundary input ports, propagating downstream through clock trees to define launch and capture edges at all register clock pins.
What To Check
- Warning sign: A port named clk exists but no clock object is created, or the waveform is wrong.
- Inspect: Start with one named object in the report and trace it to the netlist, library, or SDC statement that created it.
- Correct: Correct
create_clockin the owning SDC and confirm the reported clock and representative clock-pin timing.
Command Checks & Actions
- report_clocks: shows clock definitions and relationships
check_timing-include {no_clock}: finds missing or inconsistent timing setup
Run the commands in order. Each line answers a separate part of the check.
Healthy, Suspicious & Hard-stop Results
- Expected: Verify its source object, name, period, waveform, mode visibility, and reach to intended sequential clock pins.
- Stop before floorplanning when required logic or timing coverage is missing or unexplained.
Common Mistake
The Trap: Do not assume the check passed just because ICC2 continued. Fix or narrowly justify the named objects, then rerun the same command.
What The Interviewer Is Testing
Be ready to explain why this matters before floorplanning.
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