What is a virtual clock and why is it used?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
A virtual clock is a timing reference that has no physical source anywhere inside your block — it's not an input port, not a generated clock off internal logic, nothing you can point to on the die. It exists purely to describe timing behavior happening outside the block boundary — commonly used to model an external device's launch or capture clock when you don't have (and don't need) that device's actual clock network inside your design.
Technical Explanation
- The classic use case: your block has an input port whose data comes from some external chip. You declare a virtual clock to represent that external chip's launch clock, then use it as the reference for
set_input_delayon that port — even though the virtual clock never physically exists in your netlist. - Because it's virtual, it never needs propagation, insertion delay, or a real source pin — it's purely a timing bookkeeping device for interface constraints.
- Don't confuse a virtual clock with a generated clock: a generated clock is derived from a real master clock inside the design; a virtual clock has no master and no physical presence at all.
Visual Verification
A virtual clock has no physical source pin inside the block; it serves as an external reference time base for set_input_delay and set_output_delay on boundary I/O ports.
What To Check
- Warning sign: I/O delays reference a missing or inappropriate internal clock.
- Inspect: Start with one named object in the report and trace it to the netlist, library, or SDC statement that created it.
- Correct: Create the specified virtual reference in the correct mode and verify each boundary constraint uses it intentionally.
Command Checks & Actions
- report_clocks: shows clock definitions and relationships
- report_ports -input_delay [get_ports *]: shows boundary constraints and electrical assumptions
- report_ports -output_delay [get_ports *]: shows boundary constraints and electrical assumptions
Run the commands in order. Each line answers a separate part of the check.
Healthy, Suspicious & Hard-stop Results
- Expected: A virtual clock has no physical design source and commonly represents an external launch or capture reference for I/O timing.
- Stop before floorplanning when required logic or timing coverage is missing or unexplained.
Common Mistake
The Trap: Do not assume the check passed just because ICC2 continued. Fix or narrowly justify the named objects, then rerun the same command.
What The Interviewer Is Testing
Be ready to explain why this matters before floorplanning.
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