What information does a Liberty timing library provide?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
A Liberty (.lib) library is essentially a cell's complete behavioral datasheet — how it behaves electrically and logically under specific characterized conditions — used for timing, power analysis, and picking legal cells during synthesis/optimization. It is not a placement or layout drawing. Core content includes: cell and pin names, pin directions, Boolean function, input pin capacitance, timing arcs, output transition behavior, and electrical limits (max cap, max transition).
Technical Explanation
- A Liberty (
.lib) library is essentially a cell's complete behavioral datasheet — how it behaves electrically and logically under specific characterized conditions — used for timing, power analysis, and picking legal cells during synthesis/optimization. It is not a placement or layout drawing. - Core content includes: cell and pin names, pin directions, Boolean function, input pin capacitance, timing arcs, output transition behavior, and electrical limits (max cap, max transition).
- Sequential cells get extra content on top — setup/hold constraints, and where applicable recovery/removal or pulse-width checks — because a flop's timing behavior can't be described by combinational delay arcs alone.
- Delay is usually modeled as a function of input transition and output load (a lookup table), though more advanced formats capture richer waveform behavior — so don't assume every library is a simple small 2-D table; some carry much more detail.
- Characterization is tied to specific operating conditions and the library's own modeling conventions — the same physical cell can look meaningfully different in a slow-corner
.libversus a fast-corner.lib, and mixing them up produces plausible-but-wrong timing. - Power content (leakage, internal power) is also characterized per cell, but accurate dynamic power still depends on switching activity, voltage, capacitance, and the analysis setup — the library alone doesn't give you a dynamic power number without that context.
- Practically: the important audit checks are cell coverage, matching pins/functions between library and netlist, consistent units, correct operating conditions, and compatibility with the physical (LEF/NDM) views — a
.dbfile existing on disk is not proof the active scenario is actually using it.
Visual Verification
A Liberty (.lib) timing model acts as an electrical datasheet, annotating standard cells with pin capacitances, non-linear delay lookup tables (NLDM), transition limits, and leakage power values.
Command Checks & Actions
create_lib -ref_libs {../LIBS/lib_C ../STND/stdhvt.ndm}Attaches the .lib-derived NDM library whose timing and power lookup tables delay calculation will use for every cell in the design.
report_libLists which libraries are actually loaded and their purpose scope (cts, hold, optimization, dont_use). Confirms the Liberty data you think is active is the Liberty data the tool is actually using.
set_lib_cell_purpose -include {optimization} <lib_cells>Restricts which library cells optimization is allowed to use. Since a dont_use cell is excluded from selection entirely, this turns a Liberty library's raw cell list into the actually-usable subset.
Common Mistake
The Trap: Saying Liberty contains final wire routes or that a single nominal delay is valid for every load and slew.
Follow-up Question & Model Response
"Can one physical cell have several timing views?"
Candidate Model Response: Yes; the same layout can be characterized for multiple process, voltage, and temperature conditions.
Practical Example
Tapeout Scenario: An inverter may be quick when it drives one nearby input and slower when it drives many loads. The timing model helps the tool evaluate that difference; its physical view tells the placer how much space the inverter occupies.
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