What should drive initial macro placement?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
Macro placement isn't an aesthetic exercise — it should follow the actual dataflow: which macros talk to which, how critical that connection is, and where the I/O and clock/reset sources sit. Picture "fly lines" (rubber-band connectivity lines) stretched between macros and ports — a good placement is one where those lines are short and unobstructed, giving wires a direct, legal corridor instead of a scenic detour.
Technical Explanation
- Bus sharing, power-domain membership, and required pin sides all narrow down where a macro can legally sit — placement has to respect those constraints before it can even start optimizing for wirelength.
- There's no single "correct" strategy — edge-biased, grouped, arrayed, channeled, abutted, or freeform layouts are all legitimate starting points; the right one depends on the design, and you validate it by testing, not by assuming a pattern is inherently better.
Visual Verification
Placing macros along core perimeters with pins oriented toward the core interior minimizes signal wirelength, prevents central routing blockages, and preserves contiguous standard cell area.
Formula Or Decision Rule
Decision rule: every macro location should have a named functional reason and measurable physical consequence.
What To Check
- Warning sign: Flylines cross the core, facing pins crowd a narrow channel, or critical paths detour around macros.
- Inspect: choose one affected region, macro, row, pin, path, or net and trace the physical cause.
- Correct: Move or orient macros to reduce the diagnosed conflict, then repeat congestion, pin-access, and timing estimates.
Command Checks & Actions
- create_placement -floorplan -timing_driven -congestion: runs early floorplan placement when -floorplan is used
report_design-floorplan: reports the floorplan state understood by the tool
Run only the commands needed for this question. Save the report with the floorplan version and analysis context.
Healthy, Suspicious & Hard-stop Results
- Healthy: Connectivity, dataflow, timing criticality, I/O affinity, bus sharing, clock/reset sources, power domains, pin sides, and macro dimensions should drive placement.
- Hard stop: required legality or physical feasibility is missing or unexplained.
Common Mistake
The Trap: Do not hide the symptom with an arbitrary utilisation, halo, channel, blockage, pin move, or die-size change.
What The Interviewer Is Testing
” to measurable physical evidence and an owned correction.
Physical Design & Planning Handbook
Master ASIC Physical Design Planning & Floorplanning
Dive into 14 comprehensive chapters covering netlist sanity, FinFET grids, macro placement, power grids, CTS, and timing budgeting.
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