How does a hard macro differ from a standard cell during floorplanning?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
A hard macro (think SRAM or a hardened IP block) arrives with its size, shape, and pin locations frozen โ it's furniture, not something you can reshape to fit the room. A standard cell is tiny and numerous by comparison โ thousands of interchangeable Lego bricks that get arranged later, inside whatever legal rows the macro layout leaves behind.
Technical Explanation
- That size asymmetry drives sequencing: move one memory macro a few hundred microns and you can reroute kilometers of aggregate wire across the whole chip, but nudging one standard cell almost never changes the floorplan's shape.
- Because of that leverage, macro dimensions, which sides carry pins, allowed orientations, power-pin locations, and internal hierarchy all have to be locked in early โ standard-cell placement is deliberately deferred until the macros (and their channels) are settled.
Visual Verification
Hard macros are large, inflexible pre-designed IP blocks (SRAMs, PLLs) with fixed internal routing and boundary pins, whereas standard cells are small, flexible building blocks.
Formula Or Decision Rule
Decision rule: place the least flexible, highest-impact objects first while preserving dataflow and access.
What To Check
- Warning sign: Macros are treated like large movable standard cells and scattered without channel planning.
- Inspect: choose one affected region, macro, row, pin, path, or net and trace the physical cause.
- Correct: Use connectivity, pin geometry, timing, power domains, and access to create a deliberate macro plan.
Command Checks & Actions
report_design-floorplan: reports the floorplan state understood by the tool
Run only the commands needed for this question. Save the report with the floorplan version and analysis context.
Healthy, Suspicious & Hard-stop Results
- Healthy: A hard macro has fixed dimensions and pin geometry, so its placement strongly shapes channels and rows. Standard cells are small, numerous, and placed later within legal rows.
- Hard stop: required legality or physical feasibility is missing or unexplained.
Common Mistake
The Trap: Do not hide the symptom with an arbitrary utilisation, halo, channel, blockage, pin move, or die-size change.
What The Interviewer Is Testing
โ to measurable physical evidence and an owned correction.
Physical Design & Planning Handbook
Master ASIC Physical Design Planning & Floorplanning
Dive into 14 comprehensive chapters covering netlist sanity, FinFET grids, macro placement, power grids, CTS, and timing budgeting.
Offline PDF Bundle
Want all 1109 questions offline?
Get the complete 4-book PDF bundle (PnR, STA, MMMC, Low Power) with a clickable table of contents - no ads, no internet needed.

Continue practising