What is a strong final input-readiness checklist for physical design?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
A real readiness review isn't a file checklist — it's asking whether the next stage can start reproducibly, with complete and internally consistent intent, and recording evidence and ownership wherever something's still unresolved. Check identity and connectivity first: approved top module and revision, matching libraries and macros, all references actually resolved, design counts as expected, and every connectivity warning explained rather than ignored.
Technical Explanation
- A real readiness review isn't a file checklist — it's asking whether the next stage can start reproducibly, with complete and internally consistent intent, and recording evidence and ownership wherever something's still unresolved.
- Check identity and connectivity first: approved top module and revision, matching libraries and macros, all references actually resolved, design counts as expected, and every connectivity warning explained rather than ignored.
- Check physical setup next — process stack, scale, sites, rows, layers, macro views, and any imported floorplan — and confirm imported physical objects genuinely match the netlist you're pairing them with.
- Then check timing and power intent: complete clocks and interfaces, exceptions reviewed (not just present), the right modes/corners/scenarios active with the right analysis types enabled, matching logical and RC models, and justified electrical assumptions — plus, where relevant, verified UPF application, annotated scan chains and test modes, and representative switching activity. Close it out with reproducibility: a manifest of exact input paths/revisions or checksums, the tool release, setup scripts, import logs, coverage reports, and a saved initial database — a readiness review doesn't require zero initial violations, it requires that the violations you do have are meaningful and the problem is correctly defined.
Command Checks & Actions
check_design -checks {netlist unbound dp_pre_floorplan}The design-readiness gate a handoff should pass before floorplanning is allowed to start.
check_timingThe timing-setup completeness gate that belongs alongside check_design in any real handoff checklist.
report_analysis_coverage -status_details {untested}Confirms nothing was silently skipped in either of the checks above, closing the loop between "the checks ran" and "the checks actually covered everything they needed to."
Common Mistake
The Trap: Demanding zero timing violations before placement, while ignoring missing constraints or undocumented input substitutions.
Follow-up Question & Model Response
"How would you summarize this in an interview?"
Candidate Model Response: 'I verify what is loaded, what it applies to, which operating cases are checked, and whether someone else can reproduce the same initial design.'
Practical Example
Tapeout Scenario: The team accepts initial negative setup slack because timing optimization is the next step, but rejects an unconstrained input bus and missing SRAM slow-corner model. The first is a valid optimization target; the latter two undermine the analysis itself.
PnR Flow Mentor Guide
Master the Physical Design Implementation Flow
Read the complete 8-chapter PnR Flow Mentor Guide free on the web — library setup through placement, clock tree synthesis, routing, chip finishing, hierarchical implementation, and ECO, all the way to stream-out.
Offline PDF Bundle
Want all 1109 questions offline?
Get the complete 4-book PDF bundle (PnR, STA, MMMC, Low Power) with a clickable table of contents - no ads, no internet needed.
Continue practising