What are the main inputs required for physical design?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
Physical design needs six real inputs, not just a blueprint: the netlist (what to build), timing library models (how fast and how much power each cell uses), physical library views (each cell's real dimensions and pins), technology data (the manufacturing grid, layers, vias, rules), RC tech models (how the wiring itself behaves electrically), and SDC (the speed target and legal timing exceptions) — like handing a contractor a full kit, not just a blueprint. The netlist is only cell instances and connections — nothing about timing or size unless the matching logical library models are loaded too.
Technical Explanation
- Physical design needs six real inputs: the netlist (what to build), timing library models (how fast and how much power each cell uses), physical library views (each cell's real dimensions and pins), technology data (the manufacturing grid, layers, vias, rules), RC tech models (how the wiring itself behaves electrically), and SDC (the speed target and legal timing exceptions) — like handing a contractor a full kit, not just a blueprint.
- The netlist is only cell instances and connections — nothing about timing or size unless the matching logical library models are loaded too.
- Physical library views give each cell's real footprint, pin locations, and obstructions, which the placer and router directly consume.
- Technology data plus RC extraction models together turn geometry into something the tool can actually time — one gives the rules, the other gives the electrical behavior of interconnect built on those rules.
- Some inputs are conditional, not universal: DEF/scripts for an existing floorplan, UPF for multivoltage designs, scan-chain data for a scan-inserted design, and macro timing/physical views whenever macros are in play. Switching activity only matters if you're doing activity-based power analysis.
- In ICC2 these reference libraries typically live in NDM packages — but a clean "successful import" only proves the files loaded, not that revisions are compatible or the design is correctly constrained.
Visual Verification
The logical netlist (left) defines gate instances and net connectivity without physical dimensions, while the physical library (right) defines the exact silicon cell footprint, pin coordinates, and routing obstructions required for floorplanning and routing.
Command Checks & Actions
read_verilog design.vLoads the gate-level netlist as the connectivity input to every later PD stage. On its own this only gives instances and connections -- no timing or size data exists until the matching library models are also loaded.
create_lib -ref_libs {../LIBS/lib_C ../STND/stdhvt.ndm}Attaches the .lib/.ndm reference libraries the netlist's cells actually resolve against. A netlist can load cleanly with none of these attached, so this is the step that turns "a file was read" into "the design has real timing and physical models."
check_design -checks {netlist unbound dp_pre_floorplan}Runs the named design-readiness checks and confirms every required input -- netlist, libraries, SDC -- actually bound before floorplanning starts. This is the gate the question is really asking about: not whether files loaded, but whether they loaded correctly.
Common Mistake
The Trap: Candidates often mistakenly saying that every design must start with a routed DEF, SPEF, and GDS. Those may be later-stage outputs or restart inputs.
Follow-up Question & Model Response
"What would you inspect first if a file is present but the tool still reports missing data?"
Candidate Model Response: Check the loaded object and its coverage, not just the filename.
Practical Example
Tapeout Scenario: For a small controller, collect controller.v, the approved standard-cell NDMs, process technology data, RC models, and its SDC. Add the SRAM views if it instantiates a memory; add UPF if a domain can shut down. Record which files are supplied and which will be generated.
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