How do you read the arc-by-arc breakdown in a report_timing output to find the dominant delay contributor?
From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
report_timing (PT) prints a Point/Incr/Path table that walks down the path arc by arc, showing each cell or net arc's own incremental delay alongside the running cumulative total. To find the dominant delay contributor, scan the Incr column for the single largest jump — not the final cumulative Path value, which only tells you the total, not where it came from.
Technical Explanation
- What the three columns mean. A
report_timing(PT) path report lists every point along the path with three numbers: Point (the object name), Incr (how much delay that one arc added), and Path (the running cumulative total). - Why the final Path number alone doesn't tell you where the delay is. The last Path value is just the total arrival time — it says nothing about which single arc contributed most of it. A path with 3 ns of total delay could have that concentrated in one slow net, or spread evenly across ten cells.
- What to scan for. Reading down the Incr column for the single largest number reveals the dominant contributor directly — almost always the most efficient place to focus a fix.
- Cell arcs versus net arcs. Each row alternates between a cell arc (delay through a gate) and a net arc (the wire to the next cell's input) — which kind the dominant Incr belongs to changes what fix makes sense.
- Why this beats guessing from the total. Two paths with an identical 3.0 ns total can have different root causes — one dominated by a slow net (a routing problem), the other by a slow cell (a sizing problem) — and only the Incr column distinguishes the two.
Common Mistake
The Trap: Focusing a debug effort on the cell or net with the largest total Path value instead of the largest single Incr value.
- Path is cumulative, so later rows always show larger numbers regardless of how much delay that particular arc actually added.
- Chasing the largest Path number instead of the largest Incr number usually means "fixing" one of the last arcs in the path, which may have added almost no delay of its own.
Follow-up Question & Model Response
If the dominant Incr value belongs to a net arc rather than a cell arc, what does that usually tell you about the right fix?
Candidate Model Response: A large net arc delay usually means the wire itself is long, resistive, or heavily loaded, which points toward a physical fix — adding a buffer partway along the net, rerouting it more directly, or moving the driving and receiving cells physically closer together during placement. This is different from a large cell arc, which points toward the driving cell itself, usually meaning it needs to be upsized for more drive strength or is seeing an unexpectedly slow input transition from its own predecessor. Treating a net-dominated delay with a cell-sizing fix, or a cell-dominated delay with a rerouting fix, targets the wrong stage of the path and usually recovers little of the lost slack.
Practical Example
report_timing -path_type full_clock_expanded on a failing 500 MHz path shows six rows: a launch flop clock-to-Q arc (Incr 0.11 ns, Path 0.11 ns), a driving inverter cell arc (Incr 0.08 ns, Path 0.19 ns), a net arc to the next stage (Incr 1.35 ns, Path 1.54 ns), a buffer cell arc (Incr 0.06 ns, Path 1.60 ns), a short net arc (Incr 0.04 ns, Path 1.64 ns), and the capture flop's setup requirement. Scanning the Incr column, not the Path column, immediately identifies the 1.35 ns net arc as the dominant contributor — nearly 80% of the total delay — pointing directly at that one long, likely unbuffered wire as the place to add an intermediate buffer, rather than at any of the cells, which each contributed under 0.11 ns apiece.
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