What is cell delay?
From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
Cell delay is the time it takes a single standard cell's output to switch after its input switches, measured between the same reference points (typically each pin's 50% voltage crossing). The tool looks this number up in the cell's own Liberty library data rather than calculating it from first principles.
Technical Explanation
Cell delay isn't a fixed spec sheet number — it's a lookup that depends on the exact situation the cell finds itself in.
- Two inputs drive the lookup: input transition and output load. The library stores delay as a table indexed by how fast the input was switching (the slew) and how much capacitance the output has to drive.
- Rise and fall delays are stored separately. A gate typically doesn't take the same time to switch high-to-low as it does low-to-high, because the transistors pulling it up and pulling it down behave differently — the library captures both directions as separate tables.
- A slower input, or a heavier load, means a slower cell. Either input pushes the lookup toward a larger delay value; both together compound the effect.
- Values outside the table's range get extrapolated. If the actual load or slew falls beyond what the library's table covers, the tool extrapolates from the nearest data points — an approximation that's noticeably less accurate than a value read directly from inside the table.
Common Mistake
- The trap: treating a cell's delay as one fixed number, the way a datasheet might quote a single "typical" figure.
- It's tempting because a cell's name and drive strength do stay the same everywhere it's used in the design.
- The same cell placed in two different spots can report two very different delays, because its input slew and output load differ — the delay genuinely depends on context, not just on which cell was chosen.
Follow-up Question & Model Response
What happens when a cell's actual output load exceeds every value in its library lookup table?
Candidate Model Response: The tool doesn't refuse to compute an answer — it extrapolates beyond the table's last known data points using the same interpolation method it uses inside the table, typically a two-dimensional fit across slew and load. That extrapolated number is a real estimate, but it carries more uncertainty than an in-range lookup, since the library was never actually characterized at that load. Seeing extrapolation warnings for a cell is usually a sign the cell is overloaded and would benefit from either upsizing or a buffer, independent of what the raw delay number says.
Practical Example
Consider a small inverter driving eight fanout pins plus a long wire, well past the loading the library characterized it for. The tool's lookup falls outside the table and extrapolates a delay estimate. Replacing that inverter with a larger drive-strength version, sized for the real load, brings the lookup back inside the table and gives the tool a fully characterized, more trustworthy delay number for that stage.
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