What is net delay (interconnect delay)?
From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
Net delay (also called interconnect delay) is the time a signal takes to travel along the metal wiring between two pins, once it leaves the driving cell. It comes from the wire's own resistance and capacitance (RC), not from any transistor switching.
Technical Explanation
A timing path is really two delays stacked together: the time a gate takes to switch, plus the time the wire after it takes to carry that switch to the next pin. Net delay is the second half.
- What causes it: every routed wire has resistance (R) and capacitance (C) simply because it is a strip of metal running near other metal and near the substrate. The tool models the wire as a chain of small R and C segments, not a single lump.
- Why it is not free: a wire's RC forms a low-pass filter — the tool computes how much that filtering slows down and rounds off the signal's edge before it reaches the next pin.
- Why it dominates at small nodes: as transistors shrink, wires do not shrink their resistance at the same rate, so net delay can be a bigger share of total path delay than the cell's own switching delay.
- Where the tool gets its numbers: before routing exists, the tool estimates net delay from an approximate wire-load model; after routing, it reads exact RC values from an extracted parasitics file (SPEF).
- Layer matters: thin lower metal layers carry more resistance per micron than thick upper layers, so the same wire length can have very different delay depending on which layer it is routed on.
Common Mistake
The Trap: Treating net delay as a rounding error you can ignore until layout is done.
- Before routing, the tool is only guessing at net delay from a wire-load model, so a path that looks comfortably safe pre-layout can lose most of its slack once real wires are extracted.
- Waiting until after routing to check long, high-fanout nets means discovering the problem late, when fixing it costs a re-route instead of a small floorplan tweak.
Follow-up Question & Model Response
If a path's net delay looks unexpectedly high after routing, what would you check first?
Candidate Model Response: I would check the net's fanout and length first — a long wire feeding many receivers picks up both more resistance and more capacitance to charge. Then I would check its metal layer, since a thin lower layer carries far more resistance per micron than a thick upper one. The usual fix is a buffer partway along the wire, a layer promotion, or a wider wire — each cuts the RC the signal fights through.
Practical Example
A 900 µm bus wire on M2 (thin, resistive) shows 310 ps of net delay; the same length re-routed on M6 shows 140 ps. That gap alone can turn a marginal setup path into a violation, which is why long timing-critical buses are often forced onto upper metal layers rather than left to the router's default choice.
Complete STA Handbook
Master Signoff-Ready Static Timing Analysis
Get the complete 10-chapter STA handbook covering setup/hold margins, clock modeling, OCV/POCV, crosstalk noise, and PrimeTime closure.
Offline PDF Bundle
Want all 1109 questions offline?
Get the complete 4-book PDF bundle (PnR, STA, MMMC, Low Power) with a clickable table of contents - no ads, no internet needed.
Continue practising