BeginnerQuestion 5 of 95

What are the four categories of timing paths (reg2reg, in2reg, reg2out, in2out)?

From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide

By Tabish Iqbal, who has 9+ years of VLSI Physical Design experience

Short Answer

Every timing path in a design falls into one of four shapes, named for its startpoint and endpoint: register-to-register (reg2reg), input-to-register (in2reg), register-to-output (reg2out), and input-to-output (in2out). Each shape is constrained by a different SDC command, because each one crosses the chip boundary differently.

Four timing path shapes side by side: reg2reg, in2reg with set_input_delay, reg2out with set_output_delay, and in2out with both — Technical Reference DiagramWhat are the four categories of timing paths (reg2reg, in2reg, reg2out, in2out)?

Technical Reference DiagramWhat are the four categories of timing paths (reg2reg, in2reg, reg2out, in2out)?

Technical Explanation

Sorting paths by shape makes it obvious which SDC command has to constrain each one.

Reg2reg — internal paths. Startpoint and endpoint are both flip-flops inside the chip. The clock definition from create_clock (SDC) alone is enough to constrain these. This shape makes up the large majority of paths in a typical design.
In2reg — data entering the chip. Startpoint is a primary input port, endpoint is an internal flip-flop. set_input_delay (SDC) tells the tool how much of the clock period was already used up by delay outside the chip, before the signal even reached the port.
Reg2out — data leaving the chip. Startpoint is an internal flip-flop, endpoint is a primary output port. set_output_delay (SDC) reserves time for whatever the receiving chip on the board needs after the signal leaves.
In2out — straight feedthrough. Startpoint is an input port, endpoint is an output port, with no flip-flop in between. Both set_input_delay and set_output_delay (SDC) are needed together — or a direct set_max_delay (SDC) — because neither one alone gives the tool a full picture of the path.
Any path missing its SDC command is unconstrained, and the tool cannot check timing on a path it has no requirement for.

Common Mistake

The trap: forgetting the in2out case entirely because it has no flip-flop to remind the designer it exists.
It's easy to constrain every clock and every register but overlook a stray input-to-output bypass wire, since nothing about it looks like it needs attention.
Left unconstrained, the tool reports the path as having no timing requirement at all — meaning a genuinely slow path can go completely unchecked until it fails in the lab.

Follow-up Question & Model Response

How do you extend this to an interface where data is sampled on both clock edges, like a DDR bus?

Candidate Model Response: The same in2reg and reg2out categories still apply — the only change is which clock edge each check references. Instead of one set_input_delay, the designer adds a second one referencing the falling edge with -clock_fall, and does the same for set_output_delay on the output side. That gives the tool separate arrival and required times for the rising-edge sample and the falling-edge sample, so both halves of the double-data-rate transfer get checked correctly.

Practical Example

During pad-ring planning on one design, a JTAG bypass path connected the TDI input pin straight to the TDO output pin through a few multiplexers, with no flip-flop in between — a textbook in2out path. Left unconstrained, it showed roughly 4 ns of unmanaged delay skew. Adding set_max_delay 1.5 -from [get_ports TDI] -to [get_ports TDO] gave the tool an explicit requirement, and the path was checked and closed cleanly from then on.

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