BeginnerQuestion 6 of 95

How do you define a clock in SDC, and what does the create_clock command do?

From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide

By Tabish Iqbal, who has 9+ years of VLSI Physical Design experience

Short Answer

create_clock (SDC) is the command that tells the tool a clock exists: its period, where it enters the design, and the shape of its waveform. Without it, the tool has no reference edge to launch or capture data against, so no synchronous timing check can happen at all.

create_clock waveform: period, rise/fall edges, and the source port where the clock enters the design — Technical Reference DiagramHow do you define a clock in SDC, and what does the create_clock command do?

Technical Reference DiagramHow do you define a clock in SDC, and what does the create_clock command do?

Technical Explanation

Every setup and hold check in the design ultimately traces back to one create_clock statement.

What the command needs. At minimum it takes a period, a source object (a port or pin where the clock enters), and optionally a waveform and a name:

# [SDC]  constraints.sdc
  create_clock -name CORE_CLK -period 2.0 -waveform {0.0 1.0} [get_ports clk_in]

-period sets the clock's cycle time in the library's time units, usually nanoseconds.
-waveform {rise fall} sets when the clock rises and falls inside that period; leaving it out gives a default 50% duty cycle waveform of {0, period/2}.
The source object is where the clock physically enters the design being analyzed — a chip input port, or an internal pin if the clock originates on-chip (from a PLL output, for instance).
No source object at all defines a virtual clock — a clock that exists only on paper, used to give set_input_delay/set_output_delay (SDC) a timing reference when the real clock isn't part of this block.
What the tool does with it. Once the clock is created, the tool traces forward from the source pin through the design to find every flip-flop clock pin it reaches, and builds the launch/capture relationships that every later timing check depends on.

Common Mistake

The trap: using create_clock on the output pin of an internal divider flip-flop instead of create_generated_clock (SDC).
It seems reasonable, since the divided signal really does behave like a clock from that point onward.
But a plain create_clock there breaks the link back to the master clock, so the tool can no longer track the two clocks' shared source when removing common-path pessimism — the divided domain ends up analyzed as if it were unrelated to the clock it actually comes from.

Follow-up Question & Model Response

What happens if you define create_clock on an internal net instead of a port or a pin?

Candidate Model Response: The tool still accepts it — the clock root simply lands on whatever pin drives that net. The catch is durability: internal nets are exactly the kind of object that gets renamed or optimized away during synthesis and place-and-route. A clock definition anchored to a port or a stable pin survives those changes; one anchored to an arbitrary internal net can silently stop resolving to anything, and the tool will flag the clock as lost with no obvious warning earlier in the flow.

Practical Example

For a 1 GHz reference clock feeding a PCIe Gen4 core, the SDC line create_clock -name PCIE_REFCLK -period 1.0 -waveform {0.0 0.5} [get_ports pcie_refclk_p] sets a 1.0 ns period with a 50% duty cycle, giving every downstream register-to-register path in that domain its 1.0 ns budget to work with.

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