What is a standard cell timing library (Liberty), and what does it contain?
From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
A Liberty (.lib) library is a text file that describes exactly how every standard cell in a technology behaves — its delay, its output slew, its input pin capacitance, and its power draw — measured across the range of input slews and output loads the cell might see.
Technical Explanation
The tool has no way to know how fast a NAND gate switches unless something tells it, and that something is the Liberty library.
- Operating conditions: the header states the voltage, temperature, and process point the whole file was characterized at, since delay changes with all three.
- Cell definitions: each cell entry lists its function, its area, and which pins are inputs, outputs, or both.
- Pin data: every pin carries its own capacitance and, for outputs, its maximum allowed transition and load.
- Timing arcs: the delay and output-slew tables are two-dimensional, indexed by the input's slew and the output's load, since both change how long the cell takes to switch.
- Power data: static leakage per logic state and the switching energy per transition let power tools estimate consumption without running a full circuit simulation.
Common Mistake
The Trap: Assuming one Liberty file is enough to cover the whole signoff flow.
- Every corner — a different voltage, temperature, and process combination — needs its own Liberty file, because the same cell's delay genuinely differs across them.
- Loading the wrong corner's library, or only one library where several are needed, produces timing numbers that do not represent real silicon at the other corners.
Follow-up Question & Model Response
Why does the tool need both a rise delay table and a fall delay table for the same pin, instead of one average number?
Candidate Model Response: A gate's internal transistor network is rarely symmetric between pulling its output high and pulling it low, so the two directions genuinely take different amounts of time. An inverter built from a strong pull-down and a weaker pull-up, for instance, falls faster than it rises. Averaging the two into one number would understate delay on the slower edge, which is exactly the edge that determines whether a path violates, so the library keeps rise and fall separate all the way through the timing calculation.
Practical Example
A 2-input NAND cell's Liberty entry lists a rise delay of 45 ps at a light 2 fF load and light input slew, growing to 210 ps at a heavy 40 fF load with a sluggish input slew — a nearly 5x delay swing from the same physical cell, entirely from its lookup table's two dimensions.
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