BeginnerQuestion 34 of 95

What is a false path?

From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide

By Tabish Iqbal, who has 9+ years of VLSI Physical Design experience

Short Answer

A false path is a timing exception, declared with set_false_path (SDC), that tells the tool to stop checking both setup and hold on a path because that path can never actually be exercised in real functional operation.

A structural netlist path being excluded from both setup and hold checking by a false path exception, contrasted with a functional path left fully checked — Technical Reference DiagramWhat is a false path?

Technical Reference DiagramWhat is a false path?

Technical Explanation

STA checks every structural path it can find in the netlist, even ones that logic or intent make impossible to ever really happen, and false paths are how the designer tells the tool which ones those are.

Typical legitimate uses: paths crossing between two clocks with no fixed timing relationship, protected by a proper synchronizer; static configuration registers written once at boot and never toggled afterward; and scan or test-only logic that is disabled during normal operation.
What the exception actually does: it removes the path entirely from both setup and hold checking, as if that structural connection did not exist for timing purposes.
The danger this creates: a false path is a blind spot by design — if it is applied to a path that can actually happen functionally, any real violation there goes completely unseen.
Why the distinction between clock-domain crossings matters here: a path between two clocks that are simply unrelated in phase, but do both toggle in real operation, is not automatically a false path; it usually needs a data-path delay check instead, not a blanket removal.

Common Mistake

The Trap: Reaching for set_false_path on an asynchronous bus crossing simply because the two clocks are unrelated.

A false path removes all delay checking on that path, so nothing keeps the individual bits of a multi-bit bus arriving anywhere close together.
A max-delay exception scoped just to the data path, instead of a blanket false path, still limits how much the bits can skew apart from each other.

Follow-up Question & Model Response

What is the difference between set_false_path and set_clock_groups -asynchronous?

Candidate Model Response: set_clock_groups (SDC) with -asynchronous cuts every timing path between two entire named clock groups in one command, which is the cleaner choice when whole clock domains genuinely never need to be checked against each other. set_false_path (SDC) is usually applied to specific pins, cells, or through-points, which fits a narrower situation such as one static configuration register rather than a full clock domain. I would reach for set_clock_groups first at the domain level, and save individual set_false_path exceptions for the specific, well-justified cases underneath it.

Practical Example

A chip-mode select register, written once during boot-up and never toggled again during normal operation, has its clock pin excluded with set_false_path -from [get_pins u_mode_reg/CK]. That single line removes an artificial 1.2 ns violation on that register that would otherwise show up every signoff run, without touching any path that data actually travels through in functional use.

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