BeginnerQuestion 35 of 95

What is a multicycle path?

From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide

By Tabish Iqbal, who has 9+ years of VLSI Physical Design experience

Short Answer

A multicycle path is a timing exception, declared with set_multicycle_path (SDC), that tells the tool a path is deliberately allowed more than one clock cycle to complete, instead of the default single-cycle deadline every path is checked against.

A launch and capture clock waveform showing the default one-cycle setup and hold points, then the same waveform with setup relaxed to two cycles and hold pulled back to one — Technical Reference DiagramWhat is a multicycle path?

Technical Reference DiagramWhat is a multicycle path?

Technical Explanation

By default the tool assumes every path has exactly one clock cycle to get from launch to capture, but some logic — a wide adder or a multi-cycle datapath — is deliberately designed to take longer, and the exception tells the tool to expect that.

The default assumption: without any exception, setup is checked one cycle after launch, and hold is checked at the very same edge as launch — a 1-cycle relationship on both ends.
Relaxing setup: set_multicycle_path 2 -setup moves the setup deadline out to two cycles instead of one, giving the path roughly double the delay budget.
The trap this creates for hold: moving setup out to cycle 2 also shifts the tool's default hold-check point out to cycle 1 — one cycle later than the true launch edge — unless told otherwise.
The fix, and why it is mandatory: a matching set_multicycle_path 1 -hold pulls the hold check back to the true launch edge, cycle 0, restoring a sane hold relationship.
The general rule: for an N-cycle setup relationship, the hold multicycle value is normally (N − 1), so a 2-cycle setup pairs with a 1-cycle hold, and a 3-cycle setup would pair with a 2-cycle hold.

Common Mistake

The Trap: Applying set_multicycle_path 2 -setup and stopping there, without the matching -hold command.

The tool's default hold point silently shifts out to cycle 1 along with the setup relaxation.
That leaves an artificial hold requirement equal to almost a full clock period, which downstream tools then try to satisfy by inserting far more delay buffering than the path actually needs.

Follow-up Question & Model Response

Why does relaxing setup on a multicycle path also change the hold check, when the two seem like separate checks?

Candidate Model Response: Setup and hold are both defined relative to the same launch edge and the same declared number of cycles, so moving the setup deadline out to a later capture edge also moves which edge the tool treats as the reference point for hold. Without an explicit hold multicycle value, the tool defaults to checking hold at the cycle just before the new setup edge, which is later than the true launch edge whenever setup was relaxed past one cycle. That is exactly why the matching hold command has to be stated explicitly rather than left to the default.

Practical Example

A 3-cycle multiply path is declared with set_multicycle_path 3 -setup -from [get_pins mult_launch/CK] -to [get_pins mult_capture/D], and paired with set_multicycle_path 2 -hold on the same path. On a 1 ns clock, this gives the multiply logic a 3 ns setup budget while keeping the hold check anchored two cycles later than the naive 1-cycle default, avoiding an unnecessary 2 ns of hold buffering.

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