BeginnerQuestion 33 of 95

What is a generated clock?

From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide

By Tabish Iqbal, who has 9+ years of VLSI Physical Design experience

Short Answer

A generated clock is a clock produced inside the design itself — by a divider, a multiplexer, or a clock-gating cell — rather than arriving from an external pin. It is declared with create_generated_clock (SDC) so the tool keeps it tied to the timing of the master clock it comes from.

A master clock entering a divide-by-2 flip-flop with the generated clock output shown still tied to the master's latency and phase — Technical Reference DiagramWhat is a generated clock?

Technical Reference DiagramWhat is a generated clock?

Technical Explanation

Not every clock in a design comes straight from a pin; many are built from another clock by logic already inside the chip, and the tool needs to be told this explicitly.

Why a plain create_clock is the wrong tool here: declaring a divider's output with create_clock (SDC) makes the tool treat it as a brand-new, independent clock, which throws away its real relationship to the clock it was actually derived from.
What create_generated_clock (SDC) preserves instead: it keeps the derived clock's phase and latency tied to its master, so the tool still knows the two clocks share a common physical path.
The -source option: points to the exact pin or port where the master clock physically enters the logic that produces the generated clock — not the clock's name, but a real object in the design.
Shaping the relationship: -divide_by and -multiply_by scale the frequency, -invert flips the clock's phase, and -edges gives finer control for a divided clock whose duty cycle is not a clean 50 percent.
Why the link to the master matters downstream: losing that tie also breaks the tool's ability to give common-path credit between the two clocks later, which affects how much on-chip variation pessimism gets applied.

Common Mistake

The Trap: Passing the master clock's name to -source, instead of the physical pin or port the master clock actually enters through.

The -source option expects a real design object, such as get_pins or get_ports, not a clock name string.
Getting this wrong means the tool cannot correctly trace the generated clock's physical relationship back to its master.

Follow-up Question & Model Response

What happens if there is more than one possible logic path from the master clock to the pin where you are defining a generated clock?

Candidate Model Response: When more than one path could reach that pin, the tool cannot automatically tell which one is the intended master-to-generated relationship, so the -master_clock (SDC) option lets the designer name the exact master clock to use for that generated clock definition. Without it, the tool may pick an unintended clock or report an ambiguous reference, which can silently corrupt the timing relationship between the two domains. This situation is common on clock multiplexers, where more than one upstream clock physically reaches the same output pin depending on the selected mode.

Practical Example

A divide-by-2 flip-flop takes a 500 MHz PLL output on its clock pin and produces a 250 MHz output. Declaring that output with create_generated_clock -source [get_pins u_pll/CLK_OUT] -divide_by 2 [get_pins u_div2/Q] keeps the 250 MHz clock's latency and phase correctly tied to the 500 MHz master, instead of treating it as an unrelated clock starting from nothing.

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