What is a hold violation, and what does it mean physically?
From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
A hold violation means new data raced through the logic and reached a flip-flop's input before the flop had finished safely latching the previous value, corrupting that stored bit. Unlike a setup violation, a hold violation cannot be fixed by running the clock slower.
Technical Explanation
A hold violation is not a speed limit — it is a race the new data wins when it should have lost.
- What is physically happening: after a clock edge, the capturing flop needs a short window, its hold time, to finish isolating the value it just sampled before any new data is allowed to arrive on that same input.
- Why the clock has no escape: the launching flop and the capturing flop respond to the very same clock edge. Slowing the clock stretches the whole period, but it does not touch the tiny window right after that one edge where hold is checked — so the violation stays exactly the same size.
- Why it is fatal, not marginal: if new data blows through before the old value is safely held, the flop stores the wrong bit permanently for that cycle — there is no frequency at which this becomes safe.
- What it means for the chip: a hold violation left in place produces silicon that behaves incorrectly at any clock speed, including a clock stopped at zero — this is why hold must be completely clean, with zero violations, before tapeout.
Common Mistake
The Trap: Assuming, out of habit from setup debugging, that running the chip slower in the lab will also mask a hold failure.
- Hold is checked against the same clock edge on both ends of the path, so the clock period never appears in the hold calculation.
- Treating a hold violation like a setup violation and simply lowering frequency leaves the corrupted data path completely unfixed.
Follow-up Question & Model Response
Why does fixing a hold violation usually mean adding delay rather than removing it?
Candidate Model Response: A hold violation happens because the data path is too fast relative to the tiny window the capturing flop needs after the clock edge, so the fix has to slow that specific path down rather than speed anything up. The standard approach is inserting one or more non-inverting delay buffers on the offending path, which adds just enough delay to clear the race without changing the logic function. Engineers usually pick buffers built from a higher-threshold-voltage cell where possible, since those add delay for comparatively less leakage power than a plain low-Vt buffer would.
Practical Example
A path between two adjacent registers with almost no logic between them reports -35 ps of hold slack even though its setup slack is a healthy 0.6 ns. Inserting two delay buffers, adding about 40 ps combined, clears the hold violation and leaves the setup margin nearly untouched, since 40 ps is negligible against a multi-nanosecond clock period.
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