What is clock skew?
From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
Clock skew is the difference in arrival time between the clock edge reaching the capture flip-flop and the clock edge reaching the launch flip-flop, on the same path. It shifts how much time the data path effectively has — positive skew gives setup more room but takes room away from hold, and negative skew does the reverse.
Technical Explanation
Because setup and hold measure the gap between two clock arrivals, any difference between those two arrivals changes both checks in opposite directions.
- Skew is just a subtraction: capture clock arrival time minus launch clock arrival time, for that specific path.
- Positive skew (capture arrives later) helps setup. The capturing edge effectively moves further away in time, giving the data path a longer deadline to hit.
- Positive skew hurts hold on the very same path. The same later capture edge shrinks how long the launched data needs to stay put before it can safely change — creating more risk of a race.
- Negative skew (capture arrives earlier) does the opposite: it tightens the setup deadline but relaxes the hold requirement.
- Zero skew isn't automatically the goal. Physical design tools sometimes introduce useful skew on purpose — deliberately delaying a capture clock on a specific tight path — to borrow setup margin from a path that has plenty of hold margin to spare, closing a violation without touching the data logic at all.
Common Mistake
- The trap: assuming zero skew everywhere is always the correct design target.
- Zero skew does simplify reasoning about the design at a glance, so it's a natural default assumption.
- Modern clock tree tools deliberately introduce useful skew to close otherwise-failing high-frequency paths, borrowing margin from paths that have plenty to spare — chasing zero skew everywhere can waste an easy fix that's already available.
Follow-up Question & Model Response
What's the difference between global skew and local skew?
Candidate Model Response: Global skew is the largest latency difference between any two flops anywhere on the chip, regardless of whether those two flops ever actually exchange data. Local skew is the latency difference between two flops that are genuinely connected by a real timing path. Local skew is what setup and hold checks actually use — a chip can have large global skew between two unrelated corners of the die and still close timing cleanly, as long as the flops that actually talk to each other have small, well-controlled local skew.
Practical Example
On a high-frequency datapath where a specific reg2reg path was consistently failing setup by about 15 ps, the clock tree synthesis tool intentionally added roughly 20 ps of extra buffer delay to that path's capture clock. That gave the setup check the margin it needed, while the same path's hold check — which had comfortable slack to begin with — easily absorbed the resulting reduction.
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