BeginnerQuestion 19 of 95

What is combinational (logic) delay in a timing path?

From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide

By Tabish Iqbal, who has 9+ years of VLSI Physical Design experience

Short Answer

Combinational logic delay is the total time added by ordinary logic gates — AND, OR, XOR, multiplexers, inverters — sitting between the launch flop's output and the capture flop's input on a timing path. It's usually the single largest, and most controllable, piece of a path's total delay.

Combinational logic delay accumulating gate by gate and wire segment by wire segment between a launch flop and a capture flop — Technical Reference DiagramWhat is combinational (logic) delay in a timing path?

Technical Reference DiagramWhat is combinational (logic) delay in a timing path?

Technical Explanation

This delay is what physical design work spends most of its effort reducing, since it's shaped directly by gate choice and layout.

Each gate's delay has an intrinsic part and a loading part. The intrinsic part is the gate's own internal switching time; the loading part is the extra time charging or discharging whatever capacitance sits on its output — fanout pins plus the connecting wire.
A gate's input transition speed changes its own delay. A gate driven by a slow, lazy transition switches noticeably slower than one driven by a crisp transition — a single slow driver early in a path quietly slows every gate after it.
Delay adds up gate by gate, plus wire by wire along the path, to get the total combinational contribution.
Gates also differ in how output direction relates to input — some always match it (a buffer), some always invert it (an inverter or NAND), and some depend on the other inputs (an XOR) — which changes which delay arc the tool looks up.

Common Mistake

The trap: ignoring how much a slow input transition (slew) can inflate a gate's own delay.
It's easy to focus only on load capacitance and gate size, since those are the more obvious levers.
A gate driven by a sluggish transition can end up with several times the delay of the same gate driven by a crisp one — meaning a fix applied only to a downstream gate can miss the real cause, which is a weak driver several stages earlier.

Follow-up Question & Model Response

What are the actual techniques for reducing combinational delay on a critical path?

Candidate Model Response: Upsizing a gate gives it more drive strength, directly cutting its own switching and loading delay. Restructuring the Boolean logic can reduce how many gates a signal has to pass through in series. Swapping to a faster-switching cell library variant trims delay at some cost in leakage power. And inserting a buffer on a high-fanout net can sharpen the transition feeding the gates downstream of it, which indirectly reduces their delay too, not just the buffer's own.

Practical Example

On one critical path, a gate was measured with a 200 ps input transition and roughly three times the delay it would have had with a crisp 30 ps transition on the same input. Upsizing the cell driving that input sharpened the transition and brought the downstream gate's delay back down to close to its best-case value, without touching the gate itself.

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