IntermediateQuestion 11 of 112

How do you define a generated clock correctly, and what goes wrong if you use create_clock instead on a divided clock?

From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide

By Tabish Iqbal, who has 9+ years of VLSI Physical Design experience

Short Answer

A generated clock is one derived on-chip from a master clock — by a divider, a clock gate, a multiplexer, or an inverter. It must be defined with create_generated_clock (SDC), not create_clock (SDC), so the tool understands and preserves the exact phase relationship between the generated clock and the master clock it comes from.

Technical Reference DiagramHow do you define a generated clock correctly, and what goes wrong if you use create_clock instead on a divided clock?

Technical Explanation

  • What makes a clock "generated" rather than primary. A primary clock, defined with create_clock (SDC), comes from outside the design's own logic — an external pin or a PLL. A generated clock is built by on-chip logic operating on an existing clock: a flip-flop dividing the frequency, a clock-gating cell, a multiplexer, or an inverter.
  • Why create_generated_clock (SDC) exists. It takes a -source argument pointing back to the master clock's defining pin, plus a -divide_by/-multiply_by factor (or explicit -edges) describing how the new clock's period and phase relate to the source — which is what lets the tool understand the generated clock derives its timing from the master.
  • What goes wrong with plain create_clock. Using create_clock at the divider's output defines a brand-new, unrelated clock with no recorded connection to the master. The tool has no way to know the two share a fixed phase relationship, and may silently assume an incorrect implicit one.
  • The concrete danger: hold checks with the wrong reference. Since the divided clock's edges must line up with specific master-clock edges, any hold or setup check between the two only comes out correct when that alignment is known — which plain create_clock never establishes.
  • -edges versus -divide_by. For clean even divisions, -divide_by is simpler; for asymmetric duty cycles, -edges gives finer control by naming the exact source edges.

Common Mistake

The Trap: Defining a divided clock with plain create_clock because it "measures the same period" as what create_generated_clock would produce.

  • The period may look identical in a quick check, but the phase alignment to the master clock is not recorded at all.
  • Paths between the master and the mis-defined clock get timed as if they were unrelated domains, which typically produces wrong — often falsely pessimistic or falsely optimistic — setup and hold numbers on exactly the paths that matter most: the divider's own output going to downstream logic.

Follow-up Question & Model Response

If the design already has a real divider flip-flop, why does the tool need an SDC command at all instead of just deriving the generated clock automatically from the netlist?

Candidate Model Response: The tool can trace the divider structurally, but STA constraints are meant to be explicit and reviewable, not inferred silently from netlist shape, since the same divider circuit could in principle be used for a non-clock purpose or intentionally bypassed in some mode. create_generated_clock makes the designer state the intended relationship directly — source clock, divide factor or edges — so the constraint is auditable in the SDC file and does not depend on the tool correctly guessing intent from gate-level structure, which is exactly the kind of implicit assumption STA signoff tries to avoid.

Practical Example

A 400 MHz master clock (CLK, 2.5 ns period) feeds a toggle flip-flop that produces a 200 MHz divided clock (CLK_DIV2) with a 50% duty cycle. The correct SDC is create_generated_clock -name CLK_DIV2 -source [get_pins U_DIV/CK] -divide_by 2 [get_pins U_DIV/Q], which tells the tool CLK_DIV2's rising edge lines up with every second rising edge of CLK. If an engineer instead wrote create_clock -name CLK_DIV2 -period 5.0 [get_pins U_DIV/Q], the period would look correct in a summary report, but a hold check from a CLK-domain flop into a CLK_DIV2-domain flop would use an undefined phase relationship instead of the real, fixed 2-to-1 alignment — a class of error that typically surfaces as an unexplained hold violation that disappears the moment the clock is redefined correctly.

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