What is Static Timing Analysis (STA), and why do we need it?
From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
Static timing analysis (STA) checks every timing path in a chip design without simulating any data. It walks each path once, adds up the worst-case delays, and compares that total against the clock period. The tool does this for every path at once, so it can prove the whole chip meets its setup and hold requirements instead of just sampling a few cases.
Technical Explanation
The tool checks timing by walking the design's structure, not by running a testbench.
- No input vectors needed. The tool doesn't care what data value passes through a gate — it only cares how long the gate takes to switch. This is what "static" means: no simulation of 0s and 1s, just delay math.
- Every path, every run. Because there's no need to trigger a specific data pattern, the tool can check all paths in one pass instead of hoping a testbench happens to exercise the slowest one.
- Speed check, not logic check. STA answers "will this signal arrive on time?" It does not answer "is this the correct value?" A design with a broken adder can still report zero timing violations.
- The pass gate for tapeout. A design is signed off for manufacturing only after STA reports zero setup violations, zero hold violations, and no rule violations (like a wire switching too slowly) across every process, voltage, and temperature (PVT) corner the design must survive.
Common Mistake
- The trap: treating a clean STA report as proof the chip works.
- A new engineer sees zero violations and assumes the design is finished, because "timing passed" sounds like "the chip is correct."
- STA only proves speed, not logic. A functional bug (say, an inverted control signal) can pass STA cleanly and still produce a broken chip.
Follow-up Question & Model Response
If STA already checks every path exhaustively, why do teams still run gate-level logic simulation at all?
Candidate Model Response: Because STA only proves delay, never function. Gate-level simulation with real test vectors is still needed to confirm that a reset sequence brings the chip up correctly, that a handshake between two clock domains doesn't drop data, and that scan-based test patterns actually toggle the bits they're supposed to. None of that is delay math — it's about whether the right value shows up, which is exactly what static analysis is built to ignore.
Practical Example
Consider a design with roughly 2 million flip-flops and a 1.2 GHz clock (about 0.83 ns period). The tool walks on the order of tens of millions of register-to-register paths and finishes the full sweep in a few hours. Writing enough simulation vectors to exercise every one of those paths at its true worst case — including rare carry-chain corners in a 64-bit adder — is not realistic within a normal project schedule, which is exactly why signoff relies on the exhaustive static sweep instead.
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