VLSI Physical Design Planning & Floorplanning Handbook

Design planning in plain terms: deciding the shape of a chip before you build it

Design planning is the early stage of physical design where you decide how a large chip will be split into blocks, how big and what shape each block is, where the macros, the power network and the pins go, and how much timing each block is allowed to use. It happens before detailed implementation, so the decisions that are expensive to change later are made once, with the whole chip in view.

The nine decisions, in the order you usually make them

1. Partition the design into blocks. Decide which logic lives in which block and what crosses between them. Chapter 1 and chapter 8.
2. Split the timing constraints. Turn the chip-level constraints into a set each block owner can apply on their own, so a block does not open as a netlist with no clock. Chapter 3.
3. Size the die and core. Estimate area, then choose aspect ratio, utilisation, rows and tracks. Chapter 4.
4. Represent what is missing. Blocks and IP that are late, partial or hard are modelled well enough to plan around. Chapter 5.
5. Plan the I/O and bumps. Decide where signals and power enter the chip, on pads or flip-chip bumps. Chapter 6.
6. Shape and place blocks and macros. Set block outlines, place macros and leave keep-out margins around them. Chapter 9.
7. Plan power. Size rings, straps and the mesh for the current each region draws. Chapter 10.
8. Plan routing, clocks and pins. Reserve room for the wires between blocks and check congestion early, plan the clock trunks, then assign pins on block edges. Chapter 11, chapter 12 and chapter 13.
9. Budget timing and commit. Split the chip-level timing into block budgets so each owner has numbers to meet, then commit the blocks for implementation. Chapter 14.

What a finished plan looks like

• Every block has an outline, a set of pins and its own constraints.
• Macros are placed with keep-out margins and nothing overlaps.
• The power network meets the voltage-drop budget in every region.
• There are no unexplained congestion hot spots between blocks.
• Every block has a timing budget its owner can work to.

How plans usually go wrong

• Block work starts before the constraints are split, so blocks cannot be timed on their own.
• The die is sized from gate count alone, ignoring macros and routing space.
• Pins are assigned without looking at the neighbouring block, which creates long, slow connections.
• Power is planned late, so macros collide with straps and have to move.