What is the purpose of the pre-floorplan sanity gate?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
This gate checks whether the imported, linked netlist and its timing intent are believable enough to start floorplanning — a "do we trust this handoff" checkpoint, not a quality review. It's deliberately narrow in scope: it says nothing about placement quality or final timing results, only about whether the starting point is sound.
Technical Explanation
- A good sanity check produces named, specific objects — actual clocks found, actual unresolved references listed — not a vague pass/fail.
- It also needs to be repeatable: another engineer working from the exact same handoff package should be able to reproduce your result.
Visual Verification
Pre-floorplan sanity verification acts as a formal quality gate, validating structural integrity, linking correctness, and SDC syntax before placing macros or allocating silicon area.
What To Check
- Warning sign: The design imports cleanly but missing clocks or unresolved references make later analysis incomplete.
- Inspect: Start with one named object in the report and trace it to the netlist, library, or SDC statement that created it.
- Correct: Stop before floorplanning, correct the owning input or setup, reopen a clean checkpoint, and repeat the same evidence set.
Command Checks & Actions
check_design-checks {netlist unbound dp_pre_floorplan}: runs the selected design-readiness checkscheck_timing: finds missing or inconsistent timing setup
Run the commands in order. Each line answers a separate part of the check.
Healthy, Suspicious & Hard-stop Results
- Expected: It decides whether the imported, linked logical design and its timing intent are trustworthy enough to begin floorplanning; it does not judge placement or timing quality-of-results.
- Stop before floorplanning when required logic or timing coverage is missing or unexplained.
Common Mistake
The Trap: Do not assume the check passed just because ICC2 continued. Fix or narrowly justify the named objects, then rerun the same command.
What The Interviewer Is Testing
Be ready to explain why this matters before floorplanning.
Physical Design & Planning Handbook
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Dive into 14 comprehensive chapters covering netlist sanity, FinFET grids, macro placement, power grids, CTS, and timing budgeting.
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