How do you map an abstract UPF power switch to a real library cell with map_power_switch?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
map_power_switch (UPF) tells the tools which library cell implements an abstract switch from create_power_switch (UPF). In IEEE 1801-2015 the syntax is the switch name followed by a required -lib_cells list and an optional -port_map. Mapping picks the cell; ICC2 still has to build and connect the physical array.
Technical Explanation
- Syntax:
map_power_switch PD_COP_SW -domain PD_COP -lib_cells {HEADER_X4}(UPF). The name matches creation; ICC2 uses -domain as lookup scope and lists no -port_map. - Library cells: each cell must be defined by
define_power_switch_cell(UPF) or carry the switch attributes in Liberty. - Port association: without
-port_map, ports match by name, and any unmatched port on either side is an error. - -port_map pairs cell ports with switch ports when names differ, including control and acknowledge ports.
- Physical build:
create_power_switch_array(ICC2) orcreate_power_switch_ring(ICC2) place the cells;connect_power_switch(ICC2) chains their controls. - Map a header cell to a header-style switch: a PMOS header gates VDD, an NMOS footer gates VSS.
- Mapping is explicit, so equivalence checkers may not prove it against the RTL intent.
# [UPF] mychip.upf
map_power_switch PD_COP_SW -domain PD_COP -lib_cells {HEADER_X4}
# [ICC2] icc2_shell
report_mv_lib_cells -verbose
check_mv_designWhat To Check
- The switch name in the map matches the name in
create_power_switch. - The library cell is a real switch cell and gates the same rail as the UPF switch.
- Every port on the switch and the cell is paired, by name or by -port_map.
- The array built in ICC2 uses the mapped cell.
Command Checks & Actions
map_power_switch PD_COP_SW -domain PD_COP -lib_cells {HEADER_X4}Bind the abstract switch to a library header cell
report_mv_lib_cells -verboseConfirm the cell PG pins and switch attributes
connect_power_switchConnect the placed switch cells per the strategy
check_mv_designCheck power switch and supply rules after mapping
Healthy, Suspicious & Hard-stop Results
- Healthy (illustrative): report_mv_lib_cells shows HEADER_X4 with its PG pins as a switch cell, and
check_mv_designis clean. - Suspicious (illustrative): The map lists several cells and the array mixes them without a stated reason.
- Hard stop: The map names a switch that does not exist, or a footer cell for a header switch.
Common Mistake
The Trap: Mapping a switch name that differs from the one created, such as PF_COP_SW for PD_COP_SW.
- The map refers to no switch, so it fails or is ignored and PD_COP_SW stays without a library cell.
What The Interviewer Is Testing
- Do you know mapping selects the cell but does not place it?
- Can you explain named association versus -port_map?
Follow-up Question & Model Response
"What happens if you never map the switch?"
Candidate Model Response: The UPF still describes a legal switch, so simulation and static checks can run. Implementation, though, has no cell to build the array from unless it can pick one from the library itself. You lose control of which switch cell and drive strength end up in silicon. Map it explicitly and check the result with report_mv_lib_cells.
Practical Example
Design Scenario: (illustrative; HEADER_X4 is an illustrative cell name) PD_COP_SW is mapped to HEADER_X4, a PMOS header with ports that match the switch by name. ICC2 then builds an array of HEADER_X4 cells across the PD_COP voltage area and chains EN from cell to cell with connect_power_switch. The last cell returns PSE_ACK to U_PC. In the UPF all of these cells are still the single switch PD_COP_SW.
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